Patents by Inventor Jiansheng Xu
Jiansheng Xu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240082846Abstract: A gene sequencing reaction device, a gene sequencing system and a gene sequencing reaction method. The gene sequencing reaction device includes: a supporting platform; a dipping container disposed on the supporting platform, wherein the dipping container has a dipping reaction area, and the dipping reaction area is configured to hold a chemical reagent for gene sequencing reaction, so as to dip a sequencing chip having a DNA sample loading structure on the surface and having a DNA sample loaded thereon in the chemical reagent to perform a gene sequencing reaction; a temperature control apparatus, configured to control the temperature of the chemical reagent in the dipping reaction area; and a transfer apparatus, configured to insert the sequencing chip into the dipping reaction area or pull out the sequencing chip from the dipping reaction area.Type: ApplicationFiled: November 21, 2023Publication date: March 14, 2024Applicant: MGI Tech Co., LTD.Inventors: Wei Ma, Xun Xu, Jiabo Wu, Ming Ni, Dong Wei, Jiansheng Tang
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Publication number: 20240074244Abstract: Provided are a display panel and a display device. The display panel includes a display region and a non-display region. The display region surrounds at least part of the non-display region. The non-display region includes an element disposition region and a bank disposition region surrounding at least part of the element disposition region. The bank disposition region is provided with a bank. The display panel includes a substrate, the bank is disposed on a side of the substrate; a light-emitting layer located on a side of the bank facing away from the substrate and including a first light-emitting portion located in the bank disposition region; and a first light-shielding structure located in the bank disposition region and on a side of the first light-emitting portion facing the substrate. The first light-emitting portion and the first light-shielding structure at least partially overlap along the thickness direction of the display panel.Type: ApplicationFiled: November 6, 2023Publication date: February 29, 2024Applicant: Xiamen Tianma Display Technology Co., Ltd.Inventors: Shui HE, Liangqin XU, Jiansheng Zhong, Jinjin Yang, Ying Liu
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Patent number: 11824002Abstract: An integrated circuit structure comprises a base and a plurality of metal levels over the base. A first metal level includes a first dielectric material. The first metal level further includes a first plurality of interconnect lines in the first dielectric material, wherein the first plurality of interconnect lines in the first metal level have variable widths from relatively narrow to relatively wide, and wherein the first plurality of interconnect lines have variable heights based on the variable widths, such that a relatively wide one of the first plurality of interconnect lines has a taller height from the substrate than a relatively narrow one of the first plurality of interconnect lines, and a shorter distance to a top of the first metal level.Type: GrantFiled: June 28, 2019Date of Patent: November 21, 2023Assignee: Intel CorporationInventors: En-Shao Liu, Joodong Park, Chen-Guan Lee, Walid M. Hafez, Chia-Hong Jan, Jiansheng Xu
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Publication number: 20200411435Abstract: An integrated circuit structure comprises a base and a plurality of metal levels over the base. A first metal level includes a first dielectric material. The first metal level further includes a first plurality of interconnect lines in the first dielectric material, wherein the first plurality of interconnect lines in the first metal level have variable widths from relatively narrow to relatively wide, and wherein the first plurality of interconnect lines have variable heights based on the variable widths, such that a relatively wide one of the first plurality of interconnect lines has a taller height from the substrate than a relatively narrow one of the first plurality of interconnect lines, and a shorter distance to a top of the first metal level.Type: ApplicationFiled: June 28, 2019Publication date: December 31, 2020Inventors: En-Shao LIU, Joodong PARK, Chen-Guan LEE, Walid M. HAFEZ, Chia-Hong JAN, Jiansheng XU
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Patent number: 10593356Abstract: A magnetoresistive (MR) sensor shield shields against both down track and cross-track interference and is formed in a single deposition step. A “tail” portion of the shield is eliminated by including a non-magnetic material adjacent to opposite sides of a middle portion of the sensor stack.Type: GrantFiled: September 19, 2016Date of Patent: March 17, 2020Assignee: SEAGATE TECHNOLOGY LLCInventors: Xin Cao, Frances Paula McElhinney, Jiansheng Xu, Marcus Winston Ormston
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Patent number: 10177561Abstract: A selective protection circuit includes a current-limiting module and a control module, where the current-limiting module includes a switch unit, and the switch unit includes a first end, a second end, and a control end; the first end is connected to a positive electrode of a bus voltage of an HVDC power supply, and the second end is connected to a positive electrode of a power supply of a voltage pre-regulator circuit in a load branch connected to the current-limiting module; the control end is connected to the control module; and the control module is configured to output a control signal to the control end when a value of a total current flowing through the switch unit is greater than or equal to a preset threshold, so as to switch off the switch unit.Type: GrantFiled: August 14, 2017Date of Patent: January 8, 2019Assignee: Huawei Technologies Co., Ltd.Inventors: Zhenxing Zhang, Jiansheng Xu
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Patent number: 9916415Abstract: Disclosed are embodiments for modeling integrated circuit (IC) performance. In these embodiments, a parasitic extraction process is performed to generate a netlist that, not only accounts for various parasitics within the IC, but also accounts for substrate-generated signal distortions (e.g., substrate-generated harmonic signal distortions) that occur within the IC. During this netlist extraction process, the design layout of the IC is analyzed to identify parasitics that are to be represented in the netlist and to also identify any circuit elements with output signals that are subject to substrate-generated signal distortions. When such circuit elements are identified, signal distortion models, which were previously empirically determined and stored in a model library, which correspond to the identified circuit elements, and which account for the signal distortions, are selected from the model library and incorporated into the netlist.Type: GrantFiled: April 11, 2016Date of Patent: March 13, 2018Assignee: GLOBALFOUNDRIES INC.Inventors: Frederick G. Anderson, Michael L. Gautsch, Jean-Marc Petillat, Philippe Ramos, Randy L. Wolf, Jiansheng Xu
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Publication number: 20170346275Abstract: A selective protection circuit includes a current-limiting module and a control module, where the current-limiting module includes a switch unit, and the switch unit includes a first end, a second end, and a control end; the first end is connected to a positive electrode of a bus voltage of an HVDC power supply, and the second end is connected to a positive electrode of a power supply of a voltage pre-regulator circuit in a load branch connected to the current-limiting module; the control end is connected to the control module; and the control module is configured to output a control signal to the control end when a value of a total current flowing through the switch unit is greater than or equal to a preset threshold, so as to switch off the switch unit.Type: ApplicationFiled: August 14, 2017Publication date: November 30, 2017Inventors: Zhenxing ZHANG, Jiansheng XU
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Publication number: 20170293709Abstract: Disclosed are embodiments for modeling integrated circuit (IC) performance. In these embodiments, a parasitic extraction process is performed to generate a netlist that, not only accounts for various parasitics within the IC, but also accounts for substrate-generated signal distortions (e.g., substrate-generated harmonic signal distortions) that occur within the IC. During this netlist extraction process, the design layout of the IC is analyzed to identify parasitics that are to be represented in the netlist and to also identify any circuit elements with output signals that are subject to substrate-generated signal distortions. When such circuit elements are identified, signal distortion models, which were previously empirically determined and stored in a model library, which correspond to the identified circuit elements, and which account for the signal distortions, are selected from the model library and incorporated into the netlist.Type: ApplicationFiled: April 11, 2016Publication date: October 12, 2017Applicant: GLOBALFOUNDRIES INC.Inventors: FREDERICK G. ANDERSON, MICHAEL L. GAUTSCH, JEAN-MARC PETILLAT, PHILIPPE RAMOS, RANDY L. WOLF, JIANSHENG XU
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Patent number: 9705303Abstract: A high voltage direct current soft-start circuit is provided in which a first end of a first switch is connected to a negative electrode of a high voltage direct current, a first end of a second switch is connected to the negative electrode of the high voltage direct current, and a drive control unit is connected separately to the first switch, the second switch, and a load, where a first part of a connector is connected to the drive control unit, and upon power-on, the first part of the connector communicates with a second part of the connector, to trigger the drive control unit to drive the first switch to turn on. The drive control unit delays a preset time after driving the first switch to turn on, drives the second switch to turn on, and drives the load to start after the second switch is turned on.Type: GrantFiled: December 28, 2015Date of Patent: July 11, 2017Assignee: Huawei Technologies Co., Ltd.Inventors: Zhenxing Zhang, Jiansheng Xu, Nenghu Chen
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Publication number: 20170004852Abstract: The implementations disclosed herein allow for formation of a magnetoresistive (MR) sensor shield that shields against both down track and cross-track interference. The shield can be formed in a single deposition step. In one implementation of the disclosed technology, a “tail” portion of the shield is eliminated by including a non-magnetic material adjacent to opposite sides of a middle portion of the sensor stack.Type: ApplicationFiled: September 19, 2016Publication date: January 5, 2017Inventors: Xin Cao, Frances Paula McElhinney, Jiansheng Xu, Marcus Winston Ormston
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Patent number: 9472214Abstract: A magnetoresistive (MR) sensor shield shields against both down track and cross-track interference. The shield can be formed in a single deposition step. In one implementation of the disclosed technology, a “tail” portion of the shield is eliminated by including a non-magnetic material adjacent to opposite sides of a middle portion of the sensor stack.Type: GrantFiled: October 14, 2014Date of Patent: October 18, 2016Assignee: SEAGATE TECHNOLOGY LLCInventors: Xin Cao, Frances Paula McElhinney, Jiansheng Xu, Marcus Winston Ormston
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Patent number: 9454979Abstract: A reader sensor comprising a sensor stack and a composite top shield. The composite top shield includes a bulk shield portion and a SAF portion, the SAF portion comprising a top magnetic layered structure and a bottom magnetic layered structure with a non-magnetic layer therebetween. Each of the magnetic layered structures has at least one soft magnetic material layer bounded by layers comprising magnetic material having a magnetic moment of at least 1.4 T.Type: GrantFiled: November 13, 2015Date of Patent: September 27, 2016Assignee: SEAGATE TECHNOLOGY LLCInventors: Zhengqi Lu, Daniel Hassett, Paula McElhinney, Jiansheng Xu
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Patent number: 9368136Abstract: In accordance with one implementation of the described technology, an apparatus comprises a sensor structure including a top shield which includes a top shield synthetic antiferromagnetic layer and a bottom shield including a bottom shield synthetic antiferromagnetic layer, wherein the bottom synthetic antiferromagnetic shield layer acts as a seed layer structure.Type: GrantFiled: February 27, 2014Date of Patent: June 14, 2016Assignee: SEAGATE TECHNOLOGY LLCInventors: Zhengqi Lu, Daniel Hassett, Paula McElhinney, Jiansheng Xu
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Publication number: 20160118782Abstract: A high voltage direct current soft-start circuit is provided in which a first end of a first switch is connected to a negative electrode of a high voltage direct current, a first end of a second switch is connected to the negative electrode of the high voltage direct current, and a drive control unit is connected separately to the first switch, the second switch, and a load, where a first part of a connector is connected to the drive control unit, and upon power-on, the first part of the connector communicates with a second part of the connector, to trigger the drive control unit to drive the first switch to turn on. The drive control unit delays a preset time after driving the first switch to turn on, drives the second switch to turn on, and drives the load to start after the second switch is turned on.Type: ApplicationFiled: December 28, 2015Publication date: April 28, 2016Inventors: Zhenxing Zhang, Jiansheng Xu, Nenghu Chen
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Patent number: 9165570Abstract: A magnetic element capable of reading data may generally be configured at least with a magnetic seed lamination disposed between a data reader stack and a magnetic shield. The magnetic seed lamination may be constructed at least with one magnetic layer coupled to the bottom shield and at least one non-magnetic layer decoupling the data reader stack from the at least one magnetic layer.Type: GrantFiled: December 19, 2014Date of Patent: October 20, 2015Assignee: Seagate Technology LLCInventors: Zhengqi Lu, Ann Lynch, Daniel Hassett, Jiansheng Xu, Jae-Young Yi, Liwen Tan, Eric W. Singleton
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Publication number: 20150243307Abstract: In accordance with one implementation of the described technology, an apparatus comprises a sensor structure including a top shield which includes a top shield synthetic antiferromagnetic layer and a bottom shield including a bottom shield synthetic antiferromagnetic layer, wherein the bottom synthetic antiferromagnetic shield layer acts as a seed layer structure.Type: ApplicationFiled: February 27, 2014Publication date: August 27, 2015Applicant: Seagate Technology LLCInventors: Zhengqi Lu, Daniel Hassett, Paula McElhinney, Jiansheng Xu
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Patent number: 9087525Abstract: A magneto-resistive (MR) sensor may include a variety of individual functional layers whereby an electrical resistance throughout the layers of the sensor stack varies according to the polarity of a pinned layer within the sensor stack. A layered synthetic anti-ferromagnetic (SAF) upper shield of the MR sensor includes an upper SAF layer and a lower SAF layer separated by a shield anti-ferromagnetic (AFM) layer. The lower SAF layer is in contact with a side shield of the MR sensor, which provides a side shield biasing field to the MR sensor. The upper SAF layer separates the lower SAF layer from a top shield and/or domain control structure (DCS) magnet(s) of the MR sensor and shields the lower SAF layer and the sensor stack from DCS stray field(s), thereby reducing noise.Type: GrantFiled: October 30, 2013Date of Patent: July 21, 2015Assignee: SEAGATE TECHNOLOGY LLCInventors: Zhengqi Lu, Daniel Hassett, Paula McElhinney, Jiansheng Xu
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Publication number: 20150116868Abstract: A magneto-resistive (MR) sensor may include a variety of individual functional layers whereby an electrical resistance throughout the layers of the sensor stack varies according to the polarity of a pinned layer within the sensor stack. A layered synthetic anti-ferromagnetic (SAF) upper shield of the MR sensor includes an upper SAF layer and a lower SAF layer separated by a shield anti-ferromagnetic (AFM) layer. The lower SAF layer is in contact with a side shield of the MR sensor, which provides a side shield biasing field to the MR sensor. The upper SAF layer separates the lower SAF layer from a top shield and/or domain control structure (DCS) magnet(s) of the MR sensor and shields the lower SAF layer and the sensor stack from DCS stray field(s), thereby reducing noise.Type: ApplicationFiled: October 30, 2013Publication date: April 30, 2015Applicant: Seagate Technology LLCInventors: Zhengqi Lu, Daniel Hassett, Paula McElhinney, Jiansheng Xu
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Publication number: 20150103438Abstract: A magnetic element capable of reading data may generally be configured at least with a magnetic seed lamination disposed between a data reader stack and a magnetic shield. The magnetic seed lamination may be constructed at least with one magnetic layer coupled to the bottom shield and at least one non-magnetic layer decoupling the data reader stack from the at least one magnetic layer.Type: ApplicationFiled: December 19, 2014Publication date: April 16, 2015Inventors: Zhengqi Lu, Ann Lynch, Daniel Hassett, Jiansheng Xu, Jae-Young Yi, Liwen Tan, Eric W. Singleton