Abstract: A system and a method for performing field programmable gate array (FPGA) prototype verification on a tested circuit are provided. The system includes a packet generator, a scrambling circuit, the tested circuit and a checking circuit, wherein the scrambling circuit, the tested circuit and the checking circuit are implemented on an FPGA. The packet generator outputs multiple standard packets, wherein a length of each standard packet falls within a standard range. The scrambling circuit generates multiple scrambled packets according to the multiple standard packets to the tested circuit, to make the tested circuit generate multiple output packets according to the multiple scrambled packets, wherein a length of any scrambled packet falls outside the standard range. The checking circuit verifies operations of the tested circuit according to the multiple scrambled packets and the output packets.