Patents by Inventor Jiehui SHU

Jiehui SHU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210233934
    Abstract: One illustrative IC product disclosed herein includes an (SOI) substrate comprising a base semiconductor layer, a buried insulation layer and an active semiconductor layer positioned above the buried insulation layer. In this particular example, the IC product also includes a first region of localized high resistivity formed in the base semiconductor layer, wherein the first region of localized high resistivity has an electrical resistivity that is greater than an electrical resistivity of the material of the base semiconductor layer. The IC product also includes a first region comprising integrated circuits formed above the active semiconductor layer, wherein the first region comprising integrated circuits is positioned vertically above the first region of localized high resistivity in the base semiconductor layer.
    Type: Application
    Filed: January 28, 2020
    Publication date: July 29, 2021
    Inventors: Sipeng Gu, Jiehui Shu, Haiting Wang
  • Patent number: 11075268
    Abstract: Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. A gate structure is arranged over a channel region of a semiconductor body. A first source/drain region is coupled to a first portion of the semiconductor body, and a second source/drain region is located in a second portion the semiconductor body. The first source/drain region includes an epitaxial semiconductor layer containing a first concentration of a dopant. The second source/drain region contains a second concentration of the dopant. The channel region is positioned in the semiconductor body between the first source/drain region and the second source/drain region.
    Type: Grant
    Filed: August 15, 2019
    Date of Patent: July 27, 2021
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Jiehui Shu, Baofu Zhu, Haiting Wang, Sipeng Gu
  • Patent number: 11075298
    Abstract: One illustrative integrated circuit product disclosed herein includes a gate structure positioned above a semiconductor substrate, a source region and a drain region, both of which include an epi semiconductor material, wherein at least a portion of the epi semiconductor material in the source and drain regions is positioned in the substrate. In this example, the IC product also includes an isolation structure positioned in the substrate between the source region and the drain region, wherein the isolation structure includes a channel-side edge and a drain-side edge, wherein the channel-side edge is positioned vertically below the gate structure and wherein a portion of the substrate laterally separates the isolation structure from the epi semiconductor material in the drain region.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: July 27, 2021
    Assignee: GLOBALFOUNDRIES U.S. Inc.
    Inventors: Jiehui Shu, Judson R. Holt, Sipeng Gu, Halting Wang
  • Publication number: 20210217887
    Abstract: A transistor device that includes a single semiconductor structure having an outer perimeter and a vertical height, wherein the single semiconductor structure is at least partially defined by a trench formed in a semiconductor substrate and a first layer of material positioned on the bottom surface of the trench and around the outer perimeter of the single semiconductor structure. The device also includes a second layer of material positioned on the first layer of material and around the outer perimeter of the single semiconductor structure, a gap between the outer perimeter of the single semiconductor structure and both the first and second layers of material (when considered collectively) and an insulating sidewall spacer positioned in the gap, wherein the insulating sidewall spacer has a vertical height that is less than the vertical height of the single semiconductor structure.
    Type: Application
    Filed: January 10, 2020
    Publication date: July 15, 2021
    Inventors: Jiehui Shu, Haiting Wang, Hong Yu
  • Patent number: 11043566
    Abstract: A semiconductor device is provided that includes a substrate, an active region, a pair of gates, a plurality of semiconductor structures and a plurality of pillar structures. The active region is over the substrate. The pair of gates is formed over the active region, and each gate of the pair of gates includes a gate structure and a pair of spacer structures disposed on sidewalls of the gate structure. The plurality of semiconductor structures is arranged between the pair of gates in an alternating arrangement configuration having a first width and a second width. The first width is substantially equal to a width of the gate structure. The plurality of semiconductor structures is separated by the plurality of pillar structures.
    Type: Grant
    Filed: October 10, 2019
    Date of Patent: June 22, 2021
    Assignee: GLOBALFOUNDRIES U.S. Inc.
    Inventors: Jiehui Shu, Judson Robert Holt, Sipeng Gu, Haiting Wang
  • Publication number: 20210183997
    Abstract: A gate cut isolation including an air gap and an IC including the same are disclosed. A method of forming the gate cut isolation may include forming an opening in a dummy gate that extends over a plurality of spaced active regions, the opening positioned between and spaced from a pair of active regions. The opening is filled with a fill material, and the dummy gate is removed. A metal gate is formed in a space vacated by the dummy gate on each side of the fill material, and the fill material is removed to form a preliminary gate cut opening. A liner is deposited in the preliminary gate cut opening, creating a gate cut isolation opening, which is then sealed by depositing a sealing layer. The sealing layer closes an upper end of the gate cut isolation opening and forms the gate cut isolation including an air gap.
    Type: Application
    Filed: February 25, 2021
    Publication date: June 17, 2021
    Inventors: Hong Yu, Hui Zang, Jiehui Shu
  • Patent number: 11031389
    Abstract: The present disclosure generally relates to semiconductor devices and processing. The present disclosure also relates to semiconductor structures disposed over active regions, more particularly, via contact structures disposed over such active regions and to methods of forming such semiconductor structures.
    Type: Grant
    Filed: June 11, 2019
    Date of Patent: June 8, 2021
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Jiehui Shu, Hui Zang
  • Publication number: 20210143254
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to asymmetric source and drain structures and methods of manufacture. The structure includes: at least one gate structure; a straight spacer adjacent to the at least one gate structure; and an L-shaped spacer on a side of the at least one gate structure opposing the straight spacer, the L-shaped spacer extending a first diffusion region further away from the at least one gate structure than the straight spacer extends a second diffusion region on a second side away from the at least one gate structure.
    Type: Application
    Filed: November 7, 2019
    Publication date: May 13, 2021
    Inventors: Jiehui SHU, Rinus Tek Po LEE, Baofu ZHU
  • Patent number: 11004748
    Abstract: This disclosure relates to a method of fabricating semiconductor devices with a gate-to-gate spacing that is wider than a minimum gate-to-gate spacing and the resulting semiconductor devices. The method includes forming gate structures over an active structure, the gate structures including a first gate structure, a second gate structure, and a third gate structure. The second gate structure is between the first and third gate structures. A plurality of epitaxial structures are formed adjacent to the gate structures, wherein the second gate structure separates two epitaxial structures and the two epitaxial structures are between the first and third gate structures. The second gate structure is removed. A conductive region is formed to connect the epitaxial structures between the first and third gate structures.
    Type: Grant
    Filed: June 5, 2019
    Date of Patent: May 11, 2021
    Assignee: GLOBALFOUNDRIES U.S. Inc.
    Inventors: Sipeng Gu, Jiehui Shu, Haiting Wang
  • Patent number: 11004953
    Abstract: A method is provided for fabricating a semiconductor device structure with a short channel and long channel component having different gate dielectric layers without using lithography processes or masks. The method includes forming first and second openings having sidewalls and bottom surfaces in a dielectric layer, the first opening being narrower than the second opening. A first material layer is formed in the first and second openings. A protective layer is formed over the first material layer, wherein the protective layer covers the sidewalls and the bottom surface of the second opening. A block layer is formed to fill the second opening and cover the protective layer therein. The method further includes removing side portions of the protective layer to expose upper portions of the first material layer in the second opening. The block layer is removed from the second opening to expose the protective layer remaining in the second opening.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: May 11, 2021
    Assignee: GLOBALFOUNDRIES U.S. Inc.
    Inventors: Rinus Tek Po Lee, Hui Zang, Jiehui Shu, Hong Yu, Wei Hong
  • Publication number: 20210125984
    Abstract: A method limits lateral epitaxy growth at an N-P boundary area using an inner spacer. The method may include forming inner spacers on inner sidewalls of the inner active regions of a first polarity region (e.g., n-type) and an adjacent second polarity region (e.g., p-type) that are taller than any outer spacers on an outer sidewall of the inner active regions. During forming of semiconductor layers over the active regions (e.g., via epitaxy), the inner spacers abut and limit lateral forming of the semiconductor layer. The method generates larger semiconductor layers than possible with conventional approaches, and prevents electrical shorts between the semiconductor layers in an N-P boundary area. A structure includes the semiconductor epitaxy layers separated from one another, and abutting respective inner spacers. Any outer spacer on the inner active region is shorter than a respective inner spacer.
    Type: Application
    Filed: October 23, 2019
    Publication date: April 29, 2021
    Inventors: Judson R. Holt, Jiehui Shu
  • Publication number: 20210111264
    Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to gate structures and methods of manufacture. The method includes: forming a first gate structure and a second gate structure with gate materials; etching the gate materials within the second gate structure to form a trench; and depositing a conductive material within the trench so that the second gate structure has a metal composition different than the first gate structure.
    Type: Application
    Filed: October 11, 2019
    Publication date: April 15, 2021
    Inventors: Jiehui SHU, Sipeng GU, Haiting WANG
  • Publication number: 20210111261
    Abstract: A semiconductor device is provided that includes a substrate, an active region, a pair of gates, a plurality of semiconductor structures and a plurality of pillar structures. The active region is over the substrate. The pair of gates is formed over the active region, and each gate of the pair of gates includes a gate structure and a pair of spacer structures disposed on sidewalls of the gate structure. The plurality of semiconductor structures is arranged between the pair of gates in an alternating arrangement configuration having a first width and a second width. The first width is substantially equal to a width of the gate structure. The plurality of semiconductor structures is separated by the plurality of pillar structures.
    Type: Application
    Filed: October 10, 2019
    Publication date: April 15, 2021
    Inventors: JIEHUI SHU, JUDSON ROBERT HOLT, SIPENG GU, HAITING WANG
  • Patent number: 10971583
    Abstract: A gate cut isolation including an air gap and an IC including the same are disclosed. A method of forming the gate cut isolation may include forming an opening in a dummy gate that extends over a plurality of spaced active regions, the opening positioned between and spaced from a pair of active regions. The opening is filled with a fill material, and the dummy gate is removed. A metal gate is formed in a space vacated by the dummy gate on each side of the fill material, and the fill material is removed to form a preliminary gate cut opening. A liner is deposited in the preliminary gate cut opening, creating a gate cut isolation opening, which is then sealed by depositing a sealing layer. The sealing layer closes an upper end of the gate cut isolation opening and forms the gate cut isolation including an air gap.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: April 6, 2021
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Hong Yu, Hui Zang, Jiehui Shu
  • Patent number: 10964599
    Abstract: Methods produce integrated circuit structures that include (among other components) fins extending from a first layer, source/drain structures on the fins, source/drain contacts on the source/drain structures, an insulator on the source/drain contacts defining trenches between the source/drain contacts, gate conductors in a lower portion of the trenches adjacent the fins, a first liner material lining a middle portion and an upper portion of the trenches, a fill material in the middle portion of the trenches, and a second material in the upper portion of the trenches. The first liner material is on the gate conductors in the trenches.
    Type: Grant
    Filed: August 1, 2019
    Date of Patent: March 30, 2021
    Assignee: GLOBALFOUNDRIES U.S. Inc.
    Inventors: Asli Sirman, Jiehui Shu, Chih-Chiang Chang, Huy Cao, Haigou Huang, Jinping Liu
  • Publication number: 20210074842
    Abstract: A semiconductor device comprising a substrate with a first fin and a second fin disposed on the substrate. A gate electrode is over the first fin and the second fin. A gate-cut pedestal is positioned between the first fin and the second fin, the gate-cut pedestal having side surfaces and a top surface. A portion of the side surfaces of the gate-cut pedestal is covered by the gate electrode. The gate-cut pedestal has a height that is substantially similar to a height of the first fin or the second fin.
    Type: Application
    Filed: September 11, 2019
    Publication date: March 11, 2021
    Inventor: JIEHUI SHU
  • Patent number: 10943814
    Abstract: A method forms a trench isolation opening extending into an SOI substrate, and forms an etch stop member in a portion of the insulator layer abutting a side of the trench isolation opening. The etch stop member has a higher etch selectivity than the insulator layer of the SOI substrate. A trench isolation is formed in the trench isolation opening. A contact is formed to a portion of the semiconductor layer of the SOI substrate. The etch stop member is structured to prevent contact punch through to the base substrate of the SOI substrate.
    Type: Grant
    Filed: August 21, 2019
    Date of Patent: March 9, 2021
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Ryan W. Sporer, Jiehui Shu
  • Patent number: 10937685
    Abstract: The present disclosure generally relates to semiconductor devices and processing. The present disclosure also relates to isolation structures formed in active regions, more particularly, diffusion break structures in an active semiconductor layer of a semiconductor device. The present disclosure also relates to methods of forming such structures and replacement metal gate processes.
    Type: Grant
    Filed: June 19, 2019
    Date of Patent: March 2, 2021
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Sipeng Gu, Haiting Wang, Jiehui Shu
  • Publication number: 20210057271
    Abstract: A method forms a trench isolation opening extending into an SOI substrate, and forms an etch stop member in a portion of the insulator layer abutting a side of the trench isolation opening. The etch stop member has a higher etch selectivity than the insulator layer of the SOI substrate. A trench isolation is formed in the trench isolation opening. A contact is formed to a portion of the semiconductor layer of the SOI substrate. The etch stop member is structured to prevent contact punch through to the base substrate of the SOI substrate.
    Type: Application
    Filed: August 21, 2019
    Publication date: February 25, 2021
    Inventors: Ryan W. Sporer, Jiehui Shu
  • Publication number: 20210050425
    Abstract: A semiconductor device comprises a gate stack structure having upper and lower sidewall portions and a bottom portion. The lower sidewall portions and the bottom portion having a high-k dielectric layer and a metal electrode layer that is positioned over the high-k dielectric layer. The upper sidewall portions having low-k dielectric layers over the lower sidewall portions. The low-k dielectric layers having side surfaces that are substantially coplanar with outer side surfaces of the high-k dielectric layer and are substantially coplanar with inner side surfaces of the metal electrode layer. A metal fill layer is over the metal electrode layer and the high-k dielectric layer in the lower sidewall portions and the bottom portion and between the low-k dielectric layers.
    Type: Application
    Filed: August 13, 2019
    Publication date: February 18, 2021
    Inventors: SHESH MANI PANDEY, JIEHUI SHU