Patents by Inventor Jiehui SHU

Jiehui SHU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200161136
    Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to gate structures and methods of manufacture. The structure includes: a plurality of gate structures comprising a gate cap, sidewall spacers and source and drain regions; source and drain metallization features extending to the source and drain regions; and a liner extending along an upper portion of the sidewall spacers of at least one of the plurality of gate structures.
    Type: Application
    Filed: November 16, 2018
    Publication date: May 21, 2020
    Inventors: Jiehui SHU, Hui ZANG
  • Publication number: 20200152736
    Abstract: A gate cut isolation including an air gap and an IC including the same are disclosed. A method of forming the gate cut isolation may include forming an opening in a dummy gate that extends over a plurality of spaced active regions, the opening positioned between and spaced from a pair of active regions. The opening is filled with a fill material, and the dummy gate is removed. A metal gate is formed in a space vacated by the dummy gate on each side of the fill material, and the fill material is removed to form a preliminary gate cut opening. A liner is deposited in the preliminary gate cut opening, creating a gate cut isolation opening, which is then sealed by depositing a sealing layer. The sealing layer closes an upper end of the gate cut isolation opening and forms the gate cut isolation including an air gap.
    Type: Application
    Filed: November 13, 2018
    Publication date: May 14, 2020
    Inventors: Hong Yu, Hui Zang, Jiehui Shu
  • Patent number: 10629707
    Abstract: A finFET structure includes an insulative cap over each gate in a vicinity of a first and second self-aligned contact (SAC) to source/drain regions thereof. The insulative cap has a bulbous upper insulative cap portion selectively grown to protect gate height loss during SAC opening formation. The bulbous upper insulative cap portion may be over just gates in the vicinity of the S/D regions, and optionally, over gates in the vicinity of a gate contact.
    Type: Grant
    Filed: May 23, 2018
    Date of Patent: April 21, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Hui Zang, Ruilong Xie, Jiehui Shu
  • Publication number: 20200119001
    Abstract: Methods of manufacturing FinFETs including providing a precursor FinFET structure having a substrate with fins thereon, S/D junctions on fin tops, an STI layer on the substrate and between fins, a conformal first dielectric layer on the STI layer and S/D junctions, and a second dielectric layer on the first dielectric layer; forming a conformal third dielectric layer on the second dielectric layer and surfaces of the first dielectric layer located above the second dielectric layer; forming a fourth dielectric layer on the third dielectric layer such that third dielectric layer located between adjacent fins is exposed and such that third dielectric layer located above the adjacent fins is exposed; removing the exposed third dielectric layer and the first dielectric layer located thereunder, thereby exposing the S/D junctions; and forming a metal contact on the exposed S/D junctions and the exposed portion of the third dielectric layer between adjacent fins.
    Type: Application
    Filed: October 16, 2018
    Publication date: April 16, 2020
    Inventors: Jiehui Shu, Hui Zang, Guowei Xu, Jian Gao
  • Publication number: 20200118927
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to an anti-fuse with self-aligned via patterning and methods of manufacture. The anti-fuse includes: a lower wiring layer composed of a plurality of lower wiring structures; at least one via structure in direct contact and misaligned with a first wiring structure of the plurality of lower wiring structures and offset from a second wiring structure of the plurality of lower wiring structures; and an upper wiring layer composed of at least one upper wiring structure in direct contact with the at least one via structure.
    Type: Application
    Filed: October 16, 2018
    Publication date: April 16, 2020
    Inventors: Xiaoqiang Zhang, Guoxiang Ning, Jiehui Shu
  • Publication number: 20200111704
    Abstract: One illustrative method disclosed herein includes, among other things, forming a plurality of gate structures above a semiconductor substrate, wherein a plurality of cavities are defined between adjacent gate structures, and performing a first atomic layer deposition process to form a first stressed dielectric layer in the plurality of cavities and define a first seam in each cavity of the plurality of cavities, each first seam having a height greater than a height of the adjacent gate structures.
    Type: Application
    Filed: October 4, 2018
    Publication date: April 9, 2020
    Inventors: Eric S. Kozarksy, Hong Yu, Songkram Srivathanakul, Jiehui Shu, Jinping Liu, Bryan Rice
  • Patent number: 10593757
    Abstract: Methods form an integrated circuit structure that includes complementary transistors on a first layer. An isolation structure is between the complementary transistors. Each of the complementary transistors includes source/drain regions and a gate conductor between the source/drain regions, and insulating spacers are between the gate conductor and the source/drain regions in each of the complementary transistors. With these methods and structures, an etch stop layer is formed only on the source/drain regions.
    Type: Grant
    Filed: April 25, 2018
    Date of Patent: March 17, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Jiehui Shu, Ruilong Xie, Hui Zang, Haiting Wang
  • Publication number: 20200083363
    Abstract: A device including oxide spacer in a contact over active gates (COAG) and method of production thereof. Embodiments include first gate structures over a fin of a substrate and second gate structures, each over an outer portion of the fin and a shallow trench isolation (STI) layer adjacent to the fin; a first raised source/drain (RSD) in a portion of the fin between the first gate structures and a second RSD in the portion of the fin between the first and second gate structures; a metal liner over the first and second RSD and on sidewall portions of the first and second gate structures; a metal layer over the metal liner; and an interlayer dielectric (ILD) over the metal liner and portions of the first and second gate structures.
    Type: Application
    Filed: September 10, 2018
    Publication date: March 12, 2020
    Inventors: Hui ZANG, Laertis ECONOMIKOS, Jiehui SHU, Ruilong XIE
  • Patent number: 10586860
    Abstract: In conjunction with a replacement metal gate (RMG) process for forming a fin field effect transistor (FinFET), gate isolation methods and associated structures leverage the formation of distinct narrow and wide gate cut regions in a sacrificial gate. The formation of a narrow gate cut between closely-spaced fins can decrease the extent of etch damage to interlayer dielectric layers located adjacent to the narrow gate cut by delaying the deposition of such dielectric layers until after formation of the narrow gate cut opening. The methods and resulting structures also decrease the propensity for short circuits between later-formed, adjacent gates.
    Type: Grant
    Filed: May 3, 2018
    Date of Patent: March 10, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Jiehui Shu, Laertis Economikos, Xusheng Wu, John Zhang, Haigou Huang, Hui Zhan, Tao Han, Haiting Wang, Jinping Liu, Hui Zang
  • Patent number: 10573753
    Abstract: A device including oxide spacer in a contact over active gates (COAG) and method of production thereof. Embodiments include first gate structures over a fin of a substrate and second gate structures, each over an outer portion of the fin and a shallow trench isolation (STI) layer adjacent to the fin; a first raised source/drain (RSD) in a portion of the fin between the first gate structures and a second RSD in the portion of the fin between the first and second gate structures; a metal liner over the first and second RSD and on sidewall portions of the first and second gate structures; a metal layer over the metal liner; and an interlayer dielectric (ILD) over the metal liner and portions of the first and second gate structures.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: February 25, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Hui Zang, Laertis Economikos, Jiehui Shu, Ruilong Xie
  • Patent number: 10566202
    Abstract: A method of fabricating a semiconductor device is provided, including providing sacrificial gate structures over a plurality of fins. The sacrificial gate structures include a sacrificial first gate structure and a sacrificial second gate structure. A first gate cut process is performed to form a first gate cut opening in the sacrificial first gate structure, and a second gate cut opening in the sacrificial second gate structure. A first dielectric layer is deposited in the first gate cut opening and the second gate cut opening. The first dielectric layer completely fills the first gate cut opening and partially fills the second gate cut opening. The first dielectric layer is removed from the second gate cut opening, and a second gate cut process is performed. A second dielectric layer is deposited in the second gate cut opening to form a gate cut structure.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: February 18, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Jiehui Shu, Hui Zang, Hong Yu
  • Patent number: 10566195
    Abstract: Methods of multiple patterning. First and second mandrel lines are formed on a patternable layer. Sidewall spacers are formed on the patternable layer adjacent to the first mandrel line and adjacent to the second mandrel line. A portion of the first mandrel line is removed to form a gap in the first mandrel line. A gapfill material is deposited in the gap in the first mandrel line. The gapfill material and sidewall spacers are composed of the same material.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: February 18, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Jiehui Shu, Jinping Liu, Rui Chen
  • Publication number: 20200052106
    Abstract: At least one method, apparatus, and system providing semiconductor devices comprising a first gate having a first width and comprising a first work function metal (WFM); a first liner disposed over the first WFM; a first gate metal having a first height; and a first pinch-off spacer over the first WFM, the first liner, and the first gate metal to above the first height; and a second gate having a second width greater than the first width, and comprising a second WFM; a second liner disposed over the second WFM; a second gate metal having substantially the first height; and a first conformal spacer over the second WFM and the second liner.
    Type: Application
    Filed: August 10, 2018
    Publication date: February 13, 2020
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Laertis Economikos, Hui Zang, Ruilong Xie, Neal Makela, Pei Liu, Jiehui Shu, Chih-chiang Chang
  • Publication number: 20200020687
    Abstract: Parallel fins are formed (in a first orientation), and source/drain structures are formed in or on the fins, where channel regions of the fins are between the source/drain structures. Parallel gate structures are formed to intersect the fins (in a second orientation perpendicular to the first orientation), source/drain contacts are formed on source/drain structures that are on opposite sides of the gate structures, and caps are formed on the source/drain contacts. After forming the caps, a gate cut structure is formed interrupting the portion of the gate structure that extends between adjacent fins. The upper portion of the gate cut structure includes extensions, where a first extension extends into one of the caps on a first side of the gate cut structure, and a second extension extends into the inter-gate insulator on a second side of the gate cut structure.
    Type: Application
    Filed: July 11, 2018
    Publication date: January 16, 2020
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Haiting Wang, Shesh Mani Pandey, Jiehui Shu, Laertis Economikos, Hui Zang, Ruilong Xie, Guowei Xu, Zhaoying Hu
  • Publication number: 20200002813
    Abstract: Systems and methods for depositing a material by atomic layer deposition. A first gas distribution unit is configured to provide a first precursor to a first zone inside a reaction chamber. A second gas distribution unit is configured to provide a second precursor to a second zone inside the reaction chamber. A substrate support is arranged to hold the substrates inside the reaction chamber. The substrate support is configured to linearly move the substrates relative to the reaction chamber from the first zone to the second zone as part of a cyclic deposition cycle of an atomic layer deposition process depositing the film on each of the substrates held by the substrate support.
    Type: Application
    Filed: June 29, 2018
    Publication date: January 2, 2020
    Inventors: Jiehui Shu, John H. Zhang, Jinping Liu
  • Patent number: 10522538
    Abstract: Parallel fins are formed (in a first orientation), and source/drain structures are formed in or on the fins, where channel regions of the fins are between the source/drain structures. Parallel gate structures are formed to intersect the fins (in a second orientation perpendicular to the first orientation), source/drain contacts are formed on source/drain structures that are on opposite sides of the gate structures, and caps are formed on the source/drain contacts. After forming the caps, a gate cut structure is formed interrupting the portion of the gate structure that extends between adjacent fins. The upper portion of the gate cut structure includes extensions, where a first extension extends into one of the caps on a first side of the gate cut structure, and a second extension extends into the inter-gate insulator on a second side of the gate cut structure.
    Type: Grant
    Filed: July 11, 2018
    Date of Patent: December 31, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Haiting Wang, Shesh Mani Pandey, Jiehui Shu, Laertis Economikos, Hui Zang, Ruilong Xie, Guowei Xu, Zhaoying Hu
  • Publication number: 20190393077
    Abstract: The present disclosure relates to methods for forming fill materials in trenches having different widths and related structures. A method may include: forming a first fill material in a first and second trench where the second trench has a greater width than the first trench; removing a portion of the first fill material from each trench and forming a second fill material over the first fill material; removing a portion of the first and second fill material within the second trench; and forming a third fill material in the second trench. The structure may include a first fill material in trenches having different widths wherein the upper surfaces of the first fill material in each trench are substantially co-planar. The structure may also include a second fill material on the first fill material in each trench, the second fill material having a substantially equal thickness in each trench.
    Type: Application
    Filed: June 25, 2018
    Publication date: December 26, 2019
    Inventors: Chih-Chiang Chang, Haifeng` Sheng, Jiehui Shu, Haigou Huang, Pei Liu, Jinping Liu, Haiting Wang, Daniel J. Jaeger
  • Patent number: 10510613
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a contact over an active gate structure and methods of manufacture. The structure includes: an active gate structure composed of conductive material located between sidewall material; an upper sidewall material above the sidewall material, the upper sidewall material being different material than the sidewall material; and a contact structure in electrical contact with the conductive material of the active gate structure. The contact structure is located between the sidewall material and between the upper sidewall material.
    Type: Grant
    Filed: January 23, 2018
    Date of Patent: December 17, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Jiehui Shu, Xusheng Wu, Haigou Huang, John H. Zhang, Pei Liu, Laertis Economikos
  • Publication number: 20190378751
    Abstract: A finFET device is disclosed including a fin defined in a semiconductor substrate, the fin having an upper surface and a first diffusion break positioned in the fin, wherein the first diffusion break comprises an upper surface that is substantially coplanar with the upper surface of the fin.
    Type: Application
    Filed: August 22, 2019
    Publication date: December 12, 2019
    Inventors: Jiehui Shu, Hong Yu, Jinping Liu, Hui Zang
  • Publication number: 20190371796
    Abstract: First and second fin-type field effect transistors (finFETs) are formed laterally adjacent one another extending from a top surface of an isolation layer. The first finFET has a first fin structure and the second finFET has a second fin structure. An insulator layer is on the first fin structure and the second fin structure. A gate conductor intersects the first fin structure and the second fin structure, and at least the insulator layer separates the gate conductor from the first fin structure and the second fin structure. Source and drain structures are on the first fin structure and the second fin structure laterally adjacent the gate conductor. The first fin structure has sidewalls that include a step and the second fin structure has sidewalls that do not include the step. The step is approximately parallel to the surface of the isolation layer.
    Type: Application
    Filed: May 31, 2018
    Publication date: December 5, 2019
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Hui Zang, Garo Jacques Derderian, Laertis Economikos, Chun Yu Wong, Jiehui Shu, Shesh Mani Pandey