Patents by Inventor Jim K. Nilsson
Jim K. Nilsson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10719447Abstract: Described herein are several embodiments which provide for enhanced data caching in combination with adaptive and dynamic compression to increase the storage efficiency and reduce the transmission bandwidth of data during input and output from a GPU. The techniques described herein can reduce the need to access off-chip memory, resulting in improved performance and reduced power for GPU operations. One embodiment provides for a graphics processing apparatus comprising a shader engine; one or more cache memories; cache control logic to control at least one of the one or more cache memories; and a codec unit coupled with the one or more cache memories, the codec unit configurable to perform lossless compression of read-only surface data upon storage to or eviction from the one or more cache memories.Type: GrantFiled: September 26, 2016Date of Patent: July 21, 2020Assignee: INTEL CORPORATIONInventors: Tomas G. Akenine-Moller, Prasoonkumar Surti, Altug Koker, David Puffer, Jim K. Nilsson
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Patent number: 10621691Abstract: Techniques related to graphics rendering including techniques for compression and/or decompression of graphics data by use of indexed subsets are described. In one example, compression in graphics rendering may include determining a plurality of color values associated with individual pixels of a tile of pixels, generating a subset of the plurality of color values such that the subset of the plurality of color values include one or more distinct color values from the plurality of color values, associating an index value with each color value of the subset of the plurality of color values, determining, for each of the individual pixels, an associated pixel index value to generate a plurality of pixel index value associated with the individual pixels of the tile of pixels, storing, in memory, graphics data including the subset of the plurality of color values, the associated index values, and the plurality of pixel values.Type: GrantFiled: August 31, 2016Date of Patent: April 14, 2020Assignee: INTEL CORPORATIONInventors: Prasoonkumar Surti, Tomas G. Akenine-Moller, Jon N. Hasselgren, Carl J. Munkberg, Jim. K. Nilsson
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Patent number: 10466769Abstract: In accordance with some embodiments, the knowledge that a capped frame time is used can be exploited to reduce power consumption. Generally a capped frame time is a pre-allocated amount of time to apply power for rendering in graphics processing. Generally the frame time involves the application of power and some down time in which only idle power is applied pending the next frame time. By making better use of that down time, power consumption reductions can be achieved in some embodiments.Type: GrantFiled: November 2, 2015Date of Patent: November 5, 2019Assignee: Intel CorporationInventors: Tomas G. Akenine-Moller, Bjorn Johnsson, Magnus Andersson, Jim K. Nilsson, Robert M. Toth, Carl J. Munkberg, Jon N. Hasselgren
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Patent number: 10354432Abstract: An apparatus and method are described for texture space shading. For example, one embodiment of a method comprises: performing texture mapping to map one or more textures to surfaces of one or more objects in texture space within a ray tracing architecture; and performing sampling and reconstruction directly on the surfaces of the objects in the texture space.Type: GrantFiled: April 1, 2016Date of Patent: July 16, 2019Assignee: Intel CorporationInventors: Carl J. Munkberg, Jon N. Hasselgren, Franz P. Clarberg, Magnus Andersson, Robert M. Toth, Jim K. Nilsson, Tomas G. Akenine-Moller
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Patent number: 10121264Abstract: Color values may be compressed using a palette based encoder. Clusters of color values may be identified and encoded color values within the cluster with respect to a color value having a predefined characteristic. Clusters that have pixels or samples with constant color value may also be encoded.Type: GrantFiled: September 7, 2016Date of Patent: November 6, 2018Assignee: Intel CorporationInventors: Tomas G. Akenine-Moller, Jim K. Nilsson
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Patent number: 9959643Abstract: Cache thrashing or over-accessing of a cache can be reduced by reversing the order of traversal of a triangle on different granularities. In the case where triangles are not grouped, the traverse order may be reversed on each triangle. In cases where triangles are grouped, the traversal order may be reversed with each group change. However, when motion is excessive, for example beyond a threshold, then the traversal order reversal may be disabled.Type: GrantFiled: October 29, 2015Date of Patent: May 1, 2018Assignee: Intel CorporationInventors: Jon N. Hasselgren, Tomas G. Akenine-Moller, Carl J. Munkberg, Franz P. Clarberg, Jim K. Nilsson
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Patent number: 9940733Abstract: Data destined for memory, i.e., data that was evicted at some level in the cache hierarchy is intercepted and subjected to compression before being sent to memory. Thereby, when the compression is successful, the memory bandwidth requirement is reduced, potentially resulting in higher performance and/or energy efficiency in some embodiments.Type: GrantFiled: June 26, 2014Date of Patent: April 10, 2018Assignee: Intel CorporationInventors: Jim K. Nilsson, Tomas G. Akenine-Moller
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Publication number: 20180089091Abstract: Described herein are several embodiments which provide for enhanced data caching in combination with adaptive and dynamic compression to increase the storage efficiency and reduce the transmission bandwidth of data during input and output from a GPU. The techniques described herein can reduce the need to access off-chip memory, resulting in improved performance and reduced power for GPU operations. One embodiment provides for a graphics processing apparatus comprising a shader engine; one or more cache memories; cache control logic to control at least one of the one or more cache memories; and a codec unit coupled with the one or more cache memories, the codec unit configurable to perform lossless compression of read-only surface data upon storage to or eviction from the one or more cache memories.Type: ApplicationFiled: September 26, 2016Publication date: March 29, 2018Applicant: Intel CorporationInventors: Tomas G. Akenine-Moller, Prasoonkumar Surti, Altug Koker, David Puffer, Jim K. Nilsson
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Publication number: 20180082468Abstract: Methods and apparatus relating to techniques for provision of hierarchical Z-Culling (HiZ) optimized shadow mapping are described. In an embodiment, a processor performs one or more operations on depth data of an image tile in response to a determination that the depth data includes a minimum depth value inside the image tile and a maximum depth value inside the image tile. Other embodiments are also disclosed and claimed.Type: ApplicationFiled: September 16, 2016Publication date: March 22, 2018Applicant: Intel CorporationInventors: Tomas G. Akenine-Moller, Magnus Andersson, Jon N. Hasselgren, Carl J. Munkberg, Jim K. Nilsson
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Patent number: 9922449Abstract: An apparatus and method are described for dynamic polygon or primitive sorting for improved culling. For example, one embodiment of an apparatus comprises: a rasterization unit to receive a plurality of polygons to be rasterized in an original ordering; and depth test evaluation logic to determine whether a current polygon is fully visible, partially visible or occluded; and reordering logic to incrementally alter the original ordering by swapping each occluded polygon with another polygon positioned relatively lower in the original ordering and by swapping each fully visible polygon with another polygon positioned relatively higher in the original ordering.Type: GrantFiled: June 1, 2015Date of Patent: March 20, 2018Assignee: INTEL CORPORATIONInventors: Jim K. Nilsson, Tomas G. Akenine-Moller, Magnus Andersson
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Patent number: 9906816Abstract: A mechanism is described for facilitating environment-based lossy compression of data for efficient rendering of contents at computing devices. A method of embodiments, as described herein, includes collecting, in real time, sensory input data relating to characteristics of at least one of a user and a surrounding environment. The method may further include evaluating the sensory input data to mark one or more data portions of data relating to contents, where the one or more data portions are determined to be suitable for compression based on the sensory input data. The method may further include dynamically performing, in real time, the compression of the one or more data portions, where the compression triggers loss of one or more content portions of the contents corresponding to the one or more data portions of the data.Type: GrantFiled: October 19, 2016Date of Patent: February 27, 2018Assignee: Intel CorporationInventors: Robert M. Toth, Jim K. Nilsson, Tomas G. Akenine-Moller, Franz P. Clarberg
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Patent number: 9892053Abstract: In accordance with some embodiments, compaction, as contrasted with compression, is used to reduce the footprint of a near memory. In compaction, the density of data storage within a storage device is increased. In compression, the number of bits used to represent information is reduced. Thus you can have compression while still having sparse or non-contiguously arranged storage. As a result, compression may not always reduce the memory footprint. By compacting compressed data, the footprint of the information stored within the memory may be reduced. Compaction may reduce the need for far memory accesses in some cases.Type: GrantFiled: March 24, 2015Date of Patent: February 13, 2018Assignee: Intel CorporationInventors: Jim K. Nilsson, Tomas G. Akenine-Moller, Franz P. Clarberg
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Patent number: 9886740Abstract: In one embodiment the table pointed to by visibility samples in Degradation Coverage-Based Anti-Aliasing is split up so that more values can fit (but each value uses fewer bits). This way, more values can be represented in a pixel, and this leads to better image quality in some embodiments. This also opens up the possibility of using as few as two values per pixel, whereas the CSAA uses four or more. Hence, this also saves bandwidth and therefore, also reduces power consumption in some embodiments.Type: GrantFiled: May 14, 2014Date of Patent: February 6, 2018Assignee: Intel CorporationInventors: Tomas G. Akenine-Moller, Jim K. Nilsson
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Publication number: 20180005350Abstract: Techniques related to graphics rendering including techniques for compression and/or decompression of graphics data by use of indexed subsets are described.Type: ApplicationFiled: August 31, 2016Publication date: January 4, 2018Inventors: Prasoonkumar Surti, Tomas G. Akenine-Moller, Jon N. Hasselgren, Carl J. Munkberg, Jim. K. Nilsson
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Patent number: 9754345Abstract: Techniques related to graphics rendering including techniques for compression and/or decompression of graphics data by use of pixel region bit values are described.Type: GrantFiled: March 3, 2016Date of Patent: September 5, 2017Assignee: Intel CorporationInventors: Tomas G Akenine-Moller, Jim K Nilsson, Prasoonkumar Surti, Jon N Hasselgren, Carl J Munkberg
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Patent number: 9734597Abstract: A mechanism is described for facilitating interpolated minimum-maximum compression/decompression for efficient processing of graphics data at computing devices. A method of embodiments, as described herein, includes detecting a tile having pixels representing graphics contents capable of being processed by a graphics processor of a computing device; computing a minimum color value and a maximum color value of the tile. The method may further include splitting the tile into a plurality of interpolation tiles, where each interpolation tile includes a set of pixels of one or more colors. The method may further include computing a plurality of local minimum color values for the plurality of interpolation tiles, computing, based on the plurality of local minimum values, a plurality of residuals for the plurality of interpolation tiles to reduce spreads from the plurality of interpolation tiles, and compressing the reduced plurality of interpolation tiles based on the plurality of residuals.Type: GrantFiled: December 18, 2015Date of Patent: August 15, 2017Assignee: Intel CorporationInventors: Tomas G. Akenine-Moller, Jon N. Hasselgren, Jim K. Nilsson
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Publication number: 20170206700Abstract: An apparatus and method are described for texture space shading. For example, one embodiment of a method comprises: performing texture mapping to map one or more textures to surfaces of one or more objects in texture space within a ray tracing architecture; and performing sampling and reconstruction directly on the surfaces of the objects in the texture space.Type: ApplicationFiled: April 1, 2016Publication date: July 20, 2017Inventors: CARL J. MUNKBERG, JON N. HASSELGREN, FRANZ P. CLARBERG, MAGNUS ANDERSSON, ROBERT M. TOTH, JIM K. NILSSON, TOMAS G. AKENINE-MOLLER
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Publication number: 20170178362Abstract: A mechanism is described for facilitating interpolated minimum-maximum compression/decompression for efficient processing of graphics data at computing devices. A method of embodiments, as described herein, includes detecting a tile having pixels representing graphics contents capable of being processed by a graphics processor of a computing device; computing a minimum color value and a maximum color value of the tile. The method may further include splitting the tile into a plurality of interpolation tiles, where each interpolation tile includes a set of pixels of one or more colors. The method may further include computing a plurality of local minimum color values for the plurality of interpolation tiles, computing, based on the plurality of local minimum values, a plurality of residuals for the plurality of interpolation tiles to reduce spreads from the plurality of interpolation tiles, and compressing the reduced plurality of interpolation tiles based on the plurality of residuals.Type: ApplicationFiled: December 18, 2015Publication date: June 22, 2017Applicant: INTEL CORPORATIONInventors: TOMAS G. AKENINE-MOLLER, JON N. HASSELGREN, JIM K. NILSSON
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Publication number: 20170178276Abstract: A mechanism is described for facilitating efficient clustering and compression of graphics data at computing devices. A method of embodiments, as described herein, includes detecting a tile having pixels representing graphics contents capable of being processed by a graphics processor of a computing device. The method may further include splitting the tile into a plurality of clusters, where each cluster includes a set of pixels of one or more colors. The method may further include determining a center color for each cluster of the plurality of colors, where determining further includes deciding whether the center color is classified as acceptable for compression. The method may further include compressing contents of one or more of clusters if one or more center colors of the one or more clusters are classified as acceptable.Type: ApplicationFiled: December 22, 2015Publication date: June 22, 2017Applicant: INTEL CORPORATIONInventors: TOMAS G. AKENINE-MOLLER, JIM K. NILSSON
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Patent number: 9665973Abstract: In accordance with some embodiments, depth values may be split into more and less significant bits. By so doing, some processing can be done based only on the more significant bits. Where the number of more significant bits is significantly less than the total number of bits, some memory bandwidth can be preserved. In other words, by only using the more significant bits for some of the depth buffering operations, memory bandwidth usage can be reduced, improving efficiency.Type: GrantFiled: November 20, 2012Date of Patent: May 30, 2017Assignee: Intel CorporationInventors: Jim K. Nilsson, Tomas G. Akenine-Moller