Abstract: A computer implemented method, apparatus, and computer usable program code for collecting information about threads. A thread entering a wait state is detected. Information is selectively obtained about a set of threads in the wait state using a policy to produce an action in response to the thread entering the wait state. A history containing the collected data may be saved and used to determine changes to patterns.

Abstract: A data processing system for processing instructions is shown. Instructions are received at a processor in the data processing system. If a selected indicator is associated with the instruction, counting of each event associated with the execution of the instruction is enabled.

Abstract: A method, apparatus, and computer instructions for qualifying events by types of interrupt when interrupt occurs in the processor of a data processing system. A programmable performance monitoring unit (PMU) is used to program hardware counters that collect events associated with a type of interrupt, including nested interrupts. The performance monitoring unit may also count events that occur while servicing interrupt requests based upon the state of interrupt processing. Events that are known to the performance monitoring unit such as instruction retired, TLB misses, may be counted at the same time using a number of performance monitoring counters in the performance monitoring unit.

Abstract: A computer implemented method, apparatus, and computer program product for sampling call stack information. A set of methods and a set of criteria are received. Responsive to detecting an event associated with a method in the set of methods, a determination is made as to whether the method has met a set of criteria comprising at least one of a time based metric and a hardware performance monitor counter metric. A call stack is retrieved for the method if the method has met the set of criteria. The retrieved call stack is saved in a tree.

Abstract: A computer implemented method, apparatus, and computer usable program code for monitoring and managing a stack. Usage of stack space is monitored for a plurality of threads. Usage of stack space is compared to a policy to form a comparison. An action is selectively initiated based on the comparison to the policy.

Abstract: A method, an apparatus, and a computer program product in a data processing system are presented for using hardware assistance for gathering performance information that significantly reduces the overhead in gathering such information. Performance indicators are associated with instructions or memory locations, and processing of the performance indicators enables counting of events associated with execution of those instructions or events associated with accesses to those memory locations. The performance information that has been dynamically gathered from the assisting hardware is available to the software application during runtime in order to autonomically affect the behavior of the software application, particularly to enhance its performance. For example, the counted events may be used to autonomically control an execution-path selection within the software application.

Abstract: Illustrative embodiments cover a data processing system for processing instructions and monitoring accesses to memory location ranges. An instruction for execution is identified. A determination is made as to whether the instruction is within a contiguous range of instructions. Execution information relating to the instruction is identified if the instruction is within the contiguous range of instructions. With memory location accesses, an access to a memory location is identified. A determination of whether the memory location is within a contiguous range of memory locations is made. Access information is identified if the memory location is within the contiguous range of memory locations.

Abstract: A computer implemented method, apparatus, and computer program product for executing instructions. A determination is made as to whether a set of instructions are a set of instrumentation instructions in response to identifying the set of instructions in instructions for execution. A further determination is made as to whether a processor executing the instructions is in an instrumentation mode if the set of instructions are instrumentation instructions. The processor executes the set of instrumentation instructions only if the processor is in the instrumentation mode.

Abstract: Hardware assist to autonomically patch code. The present invention provides hardware microcode to a new type of metadata to selectively identify instructions to be patched for specific performance optimization functions. The present invention also provides a new flag in the machine status register (MSR) to enable or disable a performance monitoring application or process to perform code-patching functions. If the code patching function is enabled, the application or process may patch code at run time by associating the metadata with the selected instructions. The metadata includes pointers pointing to the patch code block code. The program code may be patched autonomically without modifying original code.

Abstract: Hardware assist to autonomically patch code. The present invention provides hardware microcode to a new type of metadata to selectively identify instructions to be patched for specific performance optimization functions. The present invention also provides a new flag in the machine status register (MSR) to enable or disable a performance monitoring application or process to perform code-patching functions. If the code patching function is enabled, the application or process may patch code at run time by associating the metadata with the selected instructions. The metadata includes pointers pointing to the patch code block code. The program code may be patched autonomically without modifying original code.

Abstract: A method, apparatus, and computer instructions for determining computer flows autonomically using hardware assisted thread stack and cataloged symbolic data. When a new thread is spawned during execution of a computer program, new thread work area is allocated by the operating system in memory for storage of call stack information for the new thread. Hardware registers are set with values corresponding to the new thread work area. Upon context switch, values of the registers are saved in a context save area for future restoration. When call stack data is post-processed, the operating system or a device driver copies call stack data from the thread work areas to a consolidated buffer and each thread is mapped to a process. Symbolic data may be obtained based on the process identifier and address of the method/routine that was called/returned in the thread. Corresponding program flow is determined using retrieved symbolic data and call stack data.

Abstract: A method, apparatus, and computer instructions for qualifying events by types of interrupt when interrupt occurs in the processor of a data processing system. A programmable performance monitoring unit (PMU) is used to program hardware counters that collect events associated with a type of interrupt, including nested interrupts. The performance monitoring unit may also count events that occur while servicing interrupt requests based upon the state of interrupt processing. Events that are known to the performance monitoring unit such as instruction retired, TLB misses, may be counted at the same time using a number of performance monitoring counters in the performance monitoring unit.

Abstract: A method, apparatus, and computer instructions in a data processing system for monitoring the execution of instructions and accesses to memory locations. If an instruction is associated with a indicator, a counter associated with the instruction is incremented in response to detecting execution of the instruction. The indicator may be associated with a memory location with a counter associated with the memory location being incremented in response to an access of the memory location.

Abstract: A computer implemented method, apparatus, and computer usable program code to collect information for a system or processor having a transition between an idle state and a non-idle state to form collected system or processor information. The collected system or processor information is provided for analysis by an application. Idle counts occurring during execution of code are collected. The idle counts are provided to an application for analyzing why a processor becomes idle.

Abstract: A computer implemented method, apparatus and computer usable program code for collecting information on wait states occurring during execution of a program. Filter criteria associated with a wait state are identified. A determination is made as to whether the filter criteria are met for the wait state. Information is collected about a set of requesters associated with the wait state in response to a determination that the filter criteria have been met.

Abstract: A method, apparatus, and computer instructions for qualifying events by types of interrupt when interrupt occurs in the processor of a data processing system. A programmable performance monitoring unit (PMU) is used to program hardware counters that collect events associated with a type of interrupt, including nested interrupts. The performance monitoring unit may also count events that occur while servicing interrupt requests based upon the state of interrupt processing. Events that are known to the performance monitoring unit such as instruction retired, TLB misses, may be counted at the same time using a number of performance monitoring counters in the performance monitoring unit.

Abstract: A computer implemented method, apparatus, and computer program product for executing instructions. A determination is made as to whether a processor executing a plurality of instructions is in an instrumentation mode. The processor has a normal set of resources and an alternate set of resources in which the alternate set of resources is associated with the instrumentation mode. When a determination is made that the processor is in the instrumentation mode, the processor executes instrumentation instructions in the plurality of instructions using the alternate set of resources and executes all other instructions in the plurality of instructions using the normal set of resources.

Abstract: A computer implemented method, apparatus, and computer usable medium for gathering performance related data in a multiprocessing environment. Instrumentation code is executed on a processor that minimizes the distortion to the processor resources used to execute the program to be profiled. Data is written by the instrumentation code to a shared memory in response to an event occurring during execution of the program. The data is generated during execution of the program on the processor and the instrumentation code uses shared memory to convey the data to a profiling application running on a set of profiling processors. The data is collected by the set of profiling processors in the shared memory written by the instrumentation code.

Abstract: A computer implemented method, apparatus and computer usable program code for marking instructions for instrumentation. A plurality of instructions is presented in a graphical user interface. A user input selecting a set of instructions in the plurality of instructions for instrumentation is received through the graphical user interface. A set of instructions is marked as a set of instrumentation instructions in response to receiving the user input. The set of instructions are executed by a processor if the processor is in an instrumentation mode, and the instrumentation instructions are unexecuted if an absence of the processor being in the instrumentation mode is present.

Abstract: A computer implemented method, apparatus and computer program product for processing instructions. A determination is made as to whether an instruction is a start instrumentation instruction in response to identifying the instruction for execution while executing the instructions using a normal set of processor resources in a processor. Subsequent instructions are executed using an alternate set of processor resources until an end instrumentation instruction is encountered.