Patents by Inventor Jimmy Fort

Jimmy Fort has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100052840
    Abstract: This document discloses low variation resistor devices, methods, systems, and methods of manufacturing the same. In some implementations, a low-variation resistor can be implemented with a metal-oxide-semiconductor field-effect-transistor (“MOSFET”) operating in the triode (e.g., ohmic) region. The MOSFET can have a source that is connected to a reference voltage (e.g., ground) and a gate connected to a gate voltage source. The gate voltage source can generate a gate voltage that varies in proportion to changes in the temperature of an operating environment. The gate voltage variation can, for example, be controlled so that it offsets the changes in MOSFET resistance that are caused by changes in temperature. In some implementations, the gate voltage variation offsets the resistance variance by offsetting changes in transistor mobility that are caused by changes in temperature.
    Type: Application
    Filed: August 26, 2008
    Publication date: March 4, 2010
    Applicant: ATMEL CORPORATION
    Inventors: Jimmy Fort, Michel Cuenca
  • Publication number: 20100008159
    Abstract: A differential sense amplifier can perform data sensing using a very low supply voltage.
    Type: Application
    Filed: July 8, 2008
    Publication date: January 14, 2010
    Applicant: ATMEL CORPORATION
    Inventors: Jimmy Fort, Renaud Dura, Thierry Soude
  • Patent number: 7642815
    Abstract: A single ended sense amplifier circuit is disclosed that is operable to measure a state of a memory cell. The amplifier can track and compensate for variations in cell current via feedback to maintain precision. The amplifier can be used with low supply voltages while still providing high-speed operation.
    Type: Grant
    Filed: September 14, 2007
    Date of Patent: January 5, 2010
    Assignee: Atmel Corporation
    Inventor: Jimmy Fort
  • Patent number: 7642872
    Abstract: An oscillator circuit for use in integrated circuits. The oscillator circuit includes a delay generation circuit having a current mirror with at least a first current mirror branch and a second current mirror branch, a current source coupled to the first current mirror branch, a capacitive element coupled to the first current mirror branch; and a resistive element coupled to the second current mirror branch. The oscillator circuit further includes a plurality of inverting elements coupled in series with one another and a transconducting element coupled to an output of the plurality of inverting elements. The transconducting element is configured to discharge the capacitive element. A latching element is coupled to latch to an output signal of the plurality of inverting elements.
    Type: Grant
    Filed: May 24, 2007
    Date of Patent: January 5, 2010
    Assignee: Atmel Corporation
    Inventors: Jimmy Fort, Michel Cuenca, Daniel Payrard
  • Patent number: 7636264
    Abstract: A sense amplifier has a transimpedance amplifier capable of producing an output voltage level proportionate to a current variation sensed going into a bitline. A transconductance device is configured to produce varying bitline current in response to the transimpedance amplifier output voltage. The transconductance device is capable of utilizing the transimpedance amplifier output voltage as feedback to produce a bitline clamp voltage level. The transimpedance amplifier configured to produce an output voltage proportionate to a cell current of a selected memory cell and provide an output signal corresponding to a memory cell state. An output amplifier is coupled to the transimpedance amplifier and capable of producing an output signal level proportionate to the transimpedance amplifier output voltage.
    Type: Grant
    Filed: February 9, 2007
    Date of Patent: December 22, 2009
    Assignee: Atmel Corporation
    Inventor: Jimmy Fort
  • Publication number: 20090153232
    Abstract: A single pump stage of a multi-stage charge pump couples a first low-voltage NMOS transistor in series with a first low-voltage PMOS transistor between charge transfer capacitors. A second low-voltage NMOS transistor is coupled between the gate and the source of the first NMOS transistor. A second low-voltage PMOS transistor is coupled between the gate and the source of the first PMOS transistor. Respective boost voltages are applied to gates of the first NMOS transistor and the second PMOS transistor to minimize threshold voltage losses. A stabilizing capacitor is connected between the first NMOS transistor and the second PMOS transistor.
    Type: Application
    Filed: October 31, 2008
    Publication date: June 18, 2009
    Applicant: Atmel Corporation
    Inventors: Jimmy Fort, Fabrice Siracusa
  • Publication number: 20090108913
    Abstract: A circuit arrangement (e.g., an integrated circuit) generates a second or higher order compensation voltage to compensate for variations in operation parameters (e.g., temperature and process variations). In one aspect, the compensation voltage is applied to a MOS resistor to compensate for mobility variations of the MOS resistor by maintaining a stable equivalent resistance. The compensated MOS resistor can provide a relatively stable resistance for a variety of analog circuit applications, such as a current reference.
    Type: Application
    Filed: October 25, 2007
    Publication date: April 30, 2009
    Inventor: Jimmy Fort
  • Publication number: 20090072889
    Abstract: An improved charge pump design useful in low power applications derives an alternative voltage from a supply voltage. The design can be constructed using PMOS manufactured according to standard processes such that triple well manufacturing processes are not required. The design can incorporate control gate circuitry to increase efficiency and decrease degradation due to the threshold voltage of the transistors used.
    Type: Application
    Filed: September 14, 2007
    Publication date: March 19, 2009
    Applicant: ATMEL CORPORATION
    Inventors: Jimmy Fort, Fabrice Siracusa
  • Publication number: 20090073781
    Abstract: A single ended sense amplifier circuit is disclosed that is operable to measure a state of a memory cell. The amplifier can track and compensate for variations in cell current via feedback to maintain precision. The amplifier can be used with low supply voltages while still providing high-speed operation.
    Type: Application
    Filed: September 14, 2007
    Publication date: March 19, 2009
    Applicant: ATMEL CORPORATION
    Inventor: Jimmy Fort
  • Publication number: 20080290930
    Abstract: A single pump stage of a multi-stage charge pump couples a first low-voltage NMOS transistor in series with a first low-voltage PMOS transistor between charge transfer capacitors. A second low-voltage NMOS transistor is coupled between the gate and the source of the first NMOS transistor. A second low-voltage PMOS transistor is coupled between the gate and the source of the first PMOS transistor. Respective boost voltages are applied to gates of the first NMOS transistor and the second PMOS transistor to minimize threshold voltage losses. A stabilizing capacitor is connected between the first NMOS transistor and the second PMOS transistor.
    Type: Application
    Filed: May 25, 2007
    Publication date: November 27, 2008
    Applicant: ATMEL CORPORATION
    Inventors: Jimmy Fort, Fabrice Siracusa
  • Publication number: 20080290955
    Abstract: An oscillator circuit for use in integrated circuits. The oscillator circuit includes a delay generation circuit having a current mirror with at least a first current mirror branch and a second current mirror branch, a current source coupled to the first current mirror branch, a capacitive element coupled to the first current mirror branch; and a resistive element coupled to the second current mirror branch. The oscillator circuit further includes a plurality of inverting elements coupled in series with one another and a transconducting element coupled to an output of the plurality of inverting elements. The transconducting element is configured to discharge the capacitive element. A latching element is coupled to latch to an output signal of the plurality of inverting elements.
    Type: Application
    Filed: May 24, 2007
    Publication date: November 27, 2008
    Applicant: ATMEL CORPORATION
    Inventors: Jimmy Fort, Michel Cuenca, Daniel Payrard
  • Patent number: 7446596
    Abstract: A single pump stage of a multi-stage charge pump couples a first low-voltage NMOS transistor in series with a first low-voltage PMOS transistor between charge transfer capacitors. A second low-voltage NMOS transistor is coupled between the gate and the source of the first NMOS transistor. A second low-voltage PMOS transistor is coupled between the gate and the source of the first PMOS transistor. Respective boost voltages are applied to gates of the first NMOS transistor and the second PMOS transistor to minimize threshold voltage losses. A stabilizing capacitor is connected between the first NMOS transistor and the second PMOS transistor.
    Type: Grant
    Filed: May 25, 2007
    Date of Patent: November 4, 2008
    Assignee: Atmel Corporation
    Inventors: Jimmy Fort, Fabrice Siracusa
  • Publication number: 20080192555
    Abstract: A sense amplifier has a transimpedance amplifier capable of producing an output voltage level proportionate to a current variation sensed going into a bitline. A transconductance device is configured to produce varying bitline current in response to the transimpedance amplifier output voltage. The transconductance device is capable of utilizing the transimpedance amplifier output voltage as feedback to produce a bitline clamp voltage level. The transimpedance amplifier configured to produce an output voltage proportionate to a cell current of a selected memory cell and provide an output signal corresponding to a memory cell state. An output amplifier is coupled to the transimpedance amplifier and capable of producing an output signal level proportionate to the transimpedance amplifier output voltage.
    Type: Application
    Filed: February 9, 2007
    Publication date: August 14, 2008
    Applicant: ATMEL CORPORATION
    Inventor: Jimmy Fort
  • Patent number: 7365585
    Abstract: An apparatus and method for improving memory cell reliability is disclosed. The slew rate is reduced in an applied voltage signal used to program a memory cell when Fowler-Nordheim (FN) tunneling injection is detected. The applied programming signal is provided by a charge pump that is preferably a regulated charge pump. The charge pump is selectively controlled by a slew rate control circuit when FN tunneling injection is detected by a voltage level detection circuit at a predetermined threshold voltage level.
    Type: Grant
    Filed: August 9, 2006
    Date of Patent: April 29, 2008
    Assignee: Atmel Corporation
    Inventors: Jimmy Fort, Jean-Michel Daga
  • Patent number: 7352640
    Abstract: A sense amplifier circuit and a method for reading a memory cell. A circuit comprises a first bit line associated with a memory cell. A first input of a latch is coupled to the first bit line and a second input of the latch is coupled to a second node. There is a means for biasing the first input and the second input of the latch to a differential voltage between the first node coupled to the first bitline and the second node. There is also a means for switching the latch according to memory cell current. There is also a means for producing an output signal indicating the direction of switch. A method of reading a memory cell comprises precharging a first bit line which is associated with a memory cell. The memory cell current is driven according to the programmed state of the memory cell. Latch circuitry is biased based on a differential voltage between a first node coupled to the first bit line and a second node.
    Type: Grant
    Filed: August 9, 2006
    Date of Patent: April 1, 2008
    Assignee: Atmel Corporation
    Inventors: Jimmy Fort, Jean-Michel Daga
  • Publication number: 20080036516
    Abstract: An apparatus and method for improving memory cell reliability is disclosed. The slew rate is reduced in an applied voltage signal used to program a memory cell when Fowler-Nordheim (FN) tunneling injection is detected. The applied programming signal is provided by a charge pump that is preferably a regulated charge pump. The charge pump is selectively controlled by a slew rate control circuit when FN tunneling injection is detected by a voltage level detection circuit at a predetermined threshold voltage level.
    Type: Application
    Filed: August 9, 2006
    Publication date: February 14, 2008
    Applicant: Atmel Corporation
    Inventors: Jimmy Fort, Jean-Michel Daga
  • Publication number: 20080037345
    Abstract: A sense amplifier circuit and a method for reading a memory cell. A circuit comprises a first bit line associated with a memory cell. A first input of a latch is coupled to the first bit line and a second input of the latch is coupled to a second node. There is a means for biasing the first input and the second input of the latch to a differential voltage between the first node coupled to the first bitline and the second node. There is also a means for switching the latch according to memory cell current. There is also a means for producing an output signal indicating the direction of switch. A method of reading a memory cell comprises precharging a first bit line which is associated with a memory cell. The memory cell current is driven according to the programmed state of the memory cell. Latch circuitry is biased based on a differential voltage between a first node coupled to the first bit line and a second node.
    Type: Application
    Filed: August 9, 2006
    Publication date: February 14, 2008
    Applicant: ATMEL CORPORATION
    Inventors: Jimmy Fort, Jean-Michel Daga