Patents by Inventor Jin-Fuw Lee

Jin-Fuw Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8473885
    Abstract: A design system for designing complex integrated circuits (ICs), a method of IC design and program product therefor. A layout unit receives a circuit description representing portions in a grid and glyph format. A checking unit checks grid and glyph portions of the design. An elaboration unit generates a target layout from the checked design. A data prep unit prepares the target layout for mask making. A pattern caching unit selectively replaces portions of the design with previously cached results for improved design efficiency.
    Type: Grant
    Filed: March 7, 2012
    Date of Patent: June 25, 2013
    Assignee: International Business Machines Corporation
    Inventors: John M. Cohn, James A. Culp, Ulrich A. Finkler, Fook-Luen Heng, Mark A. Lavin, Jin Fuw Lee, Lars W. Liebmann, Gregory A. Northrop, Nakgeuon Seong, Rama N. Singh, Leon Stok, Pieter J. Woeltgens
  • Patent number: 8219943
    Abstract: A design system for designing complex integrated circuits (ICs), a method of IC design and program product therefor. A layout unit receives a circuit description representing portions in a grid and glyph format. A checking unit checks grid and glyph portions of the design. An elaboration unit generates a target layout from the checked design. A data prep unit prepares the target layout for mask making. A pattern caching unit selectively replaces portions of the design with previously cached results for improved design efficiency.
    Type: Grant
    Filed: April 17, 2009
    Date of Patent: July 10, 2012
    Assignee: International Business Machines Corporation
    Inventors: John M Cohn, James A. Culp, Ulrich A. Finkler, Fook-Luen Heng, Mark A. Lavin, Jin Fuw Lee, Lars W. Liebmann, Gregory A. Northrop, Nakgeuon Seong, Rama N. Singh, Leon Stok, Pieter J. Woeltgens
  • Publication number: 20120167029
    Abstract: A design system for designing complex integrated circuits (ICs), a method of IC design and program product therefor. A layout unit receives a circuit description representing portions in a grid and glyph format. A checking unit checks grid and glyph portions of the design. An elaboration unit generates a target layout from the checked design. A data prep unit prepares the target layout for mask making. A pattern caching unit selectively replaces portions of the design with previously cached results for improved design efficiency.
    Type: Application
    Filed: March 7, 2012
    Publication date: June 28, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: John M. Cohn, James A. Culp, Ulrich A. Finkler, Fook-Luen Heng, Mark A. Lavin, Jin Fuw Lee, Lars W. Liebmann, Gregory A. Northrop, Nakgeuon Seong, Rama N. Singh, Leon Stok, Pieter J. Woltgens
  • Patent number: 8122387
    Abstract: A method of physical design for integrated circuit (IC) chip fabrication, physical design system and program product therefor. A design shape is fragmented into segments for Optical Proximity Correction (OPC) and a harmonic mean of the segments is determined. Electrical intent is determined for the shape and a harmonic mean is determined for the segments. Segments may be moved based on a effect on the harmonic mean from moving the segments, measured using a harmonic mean cost function. Finally segmented shapes are passed to OPC.
    Type: Grant
    Filed: June 11, 2009
    Date of Patent: February 21, 2012
    Assignee: International Business Macines Corporation
    Inventors: Geng Han, Fook-Luen Heng, Jin Fuw Lee, Chao Yi Tien, legal representative, Rama N. Singh
  • Patent number: 8020120
    Abstract: A method for layout design includes steps or acts of: receiving a layout for design of an integrated circuit chip; designing mask shapes for the layout; transmitting the mask shapes to a litho simulator for generating wafer shapes; receiving the wafer shapes; calculating electrically equivalent gate lengths for the wafer shapes; analyzing the gate lengths to check for conformity against a threshold value, wherein the threshold value represents a desired value of electrically equivalent gate lengths; placing markers on the layout at those locations where the gate length violates the threshold value; and generating a histogram of gate lengths for comparing layouts for electrically equivalent gate lengths for layout quality.
    Type: Grant
    Filed: October 1, 2007
    Date of Patent: September 13, 2011
    Assignee: International Business Machines Corporation
    Inventors: Fook-Luen Heng, Mark A. Lavin, Jin-Fuw Lee, Thomas Ludwig, Rama Nand Sing, Fanchieh Yee
  • Publication number: 20110173577
    Abstract: Techniques for improving circuit design and production are provided. In one aspect, a method for virtual fabrication of a process-sensitive circuit is provided. The method comprises the following steps. Based on a physical layout diagram of the circuit, a virtual representation of the fabricated circuit is obtained that accounts for one or more variations that can occur during a circuit production process. A quality-based metric is used to project a production yield for the virtual representation of the fabricated circuit. The physical layout diagram and/or the production process are modified. The obtaining, using and modifying steps are repeated until a desired projected production yield is attained.
    Type: Application
    Filed: February 1, 2008
    Publication date: July 14, 2011
    Applicant: International Business Machines Corporation
    Inventors: Ching-Te K. Chuang, Fook-Luen Heng, Rouwaida Kanj, Keunwoo Kim, Jin-Fuw Lee, Saibal Mukhopadhyay, Sani Richard Nassif, Rama Nand Singh
  • Patent number: 7962865
    Abstract: A system and method of employing patterning process statistics to evaluate layouts for intersect area analysis includes applying Optical Proximity Correction (OPC) to the layout, simulating images formed by the mask and applying patterning process variation distributions to influence and determine corrective actions taken to improve and optimize the rules for compliance by the layout. The process variation distributions are mapped to an intersect area distribution by creating a histogram based upon a plurality of processes for an intersect area. The intersect area is analyzed using the histogram to provide ground rule waivers and optimization.
    Type: Grant
    Filed: July 17, 2008
    Date of Patent: June 14, 2011
    Assignee: International Business Machines Corporation
    Inventors: Fook-Luen Heng, Mark Alan Lavin, Jin-Fuw Lee, Chieh-yu Lin, Jawahar Pundalik Nayak, Rama Nand Singh
  • Publication number: 20100318956
    Abstract: A method of physical design for integrated circuit (IC) chip fabrication, physical design system and program product therefor. A design shape is fragmented into segments for Optical Proximity Correction (OPC) and a harmonic mean of the segments is determined. Electrical intent is determined for the shape and a harmonic mean is determined for the segments. Segments may be moved based on a effect on the harmonic mean from moving the segments, measured using a harmonic mean cost function. Finally segmented shapes are passed to OPC.
    Type: Application
    Filed: June 11, 2009
    Publication date: December 16, 2010
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Geng Han, Fook-Luen Heng, Jin Fuw Lee, Chao Yi Tien, Rama N. Singh
  • Patent number: 7831941
    Abstract: A methodology for obtaining improved prediction of CA resistance in electronic circuits and, particularly, an improved CA resistance model adapted to capture larger than anticipated “out of spec” regime. In one embodiment, a novel bucketization scheme is implemented that is codified to provide a circuit designer with considerably better design options for handling large CA variability as seen through the design manual. The tools developed for modeling the impact of CA variable resistance phenomena provide developers with a resistance model, such as conventionally known, modified with a new CA model Basis including a novel CA intrinsic resistance model, and, a novel CA layout bucketization model.
    Type: Grant
    Filed: January 2, 2008
    Date of Patent: November 9, 2010
    Assignee: International Business Machines Corporation
    Inventors: Dureseti Chidambarrao, Fook-Luen Heng, Mark A. Lavin, Jin-Fuw Lee, Rama N. Singh, Roger Y. Tsai
  • Publication number: 20090204930
    Abstract: A design system for designing complex integrated circuits (ICs), a method of IC design and program product therefor. A layout unit receives a circuit description representing portions in a grid and glyph format. A checking unit checks grid and glyph portions of the design. An elaboration unit generates a target layout from the checked design. A data prep unit prepares the target layout for mask making. A pattern caching unit selectively replaces portions of the design with previously cached results for improved design efficiency.
    Type: Application
    Filed: April 17, 2009
    Publication date: August 13, 2009
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: John M. Cohn, James A. Culp, Ulrich A. Finkler, Fook-Luen Heng, Mark A. Lavin, Jin Fuw Lee, Lars W. Liebmann, Gregory A. Northrop, Nakgeuon Seong, Rama N. Singh, Leon Stok, Pieter J. Woltgens
  • Publication number: 20090171644
    Abstract: A methodology for obtaining improved prediction of CA resistance in electronic circuits and, particularly, an improved CA resistance model adapted to capture larger than anticipated “out of spec” regime. In one embodiment, a novel bucketization scheme is implemented that is codified to provide a circuit designer with considerably better design options for handling large CA variability as seen through the design manual. The tools developed for modeling the impact of CA variable resistance phenomena provide developers with a resistance model, such as conventionally known, modified with a new CA model Basis including a novel CA intrinsic resistance model, and, a novel CA layout bucketization model.
    Type: Application
    Filed: January 2, 2008
    Publication date: July 2, 2009
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Dureseti Chidambarrao, Fook-Luen Heng, Mark A. Lavin, Jin-Fuw Lee, Rama N. Singh, Roger Y. Tsai
  • Patent number: 7536664
    Abstract: A design system for designing complex integrated circuits (ICs), a method of IC design and program product therefor. A layout unit receives a circuit description representing portions in a grid and glyph format. A checking unit checks grid and glyph portions of the design. An elaboration unit generates a target layout from the checked design. A data prep unit prepares the target layout for mask making. A pattern caching unit selectively replaces portions of the design with previously cached results for improved design efficiency.
    Type: Grant
    Filed: August 12, 2004
    Date of Patent: May 19, 2009
    Assignee: International Business Machines Corporation
    Inventors: John M. Cohn, James A. Culp, Ulrich A. Finkler, Fook-Luen Heng, Mark A. Lavin, Jin Fuw Lee, Lars W. Liebmann, Gregory A. Northrop, Nakgeuon Seong, Rama N. Singh, Leon Stok, Pieter J. Woltgens
  • Publication number: 20090089726
    Abstract: A method for layout design includes steps or acts of: receiving a layout for design of an integrated circuit chip; designing mask shapes for the layout; transmitting the mask shapes to a litho simulator for generating wafer shapes; receiving the wafer shapes; calculating electrically equivalent gate lengths for the wafer shapes; analyzing the gate lengths to check for conformity against a threshold value, wherein the threshold value represents a desired value of electrically equivalent gate lengths; placing markers on the layout at those locations where the gate length violates the threshold value; and generating a histogram of gate lengths for comparing layouts for electrically equivalent gate lengths for layout quality.
    Type: Application
    Filed: October 1, 2007
    Publication date: April 2, 2009
    Applicant: International Business Machines Corporation
    Inventors: Fook-Luen Heng, Mark A. Lavin, Jin-Fuw Lee, Thomas Ludwig, Rama Nand Singh, Fanchieh Yee
  • Publication number: 20080301624
    Abstract: A system and method of employing patterning process statistics to evaluate layouts for intersect area analysis includes applying Optical Proximity Correction (OPC) to the layout, simulating images formed by the mask and applying patterning process variation distributions to influence and determine corrective actions taken to improve and optimize the rules for compliance by the layout. The process variation distributions are mapped to an intersect area distribution by creating a histogram based upon a plurality of processes for an intersect area. The intersect area is analyzed using the histogram to provide ground rule waivers and optimization.
    Type: Application
    Filed: July 17, 2008
    Publication date: December 4, 2008
    Inventors: Fook-Luen Heng, Mark Alan Lavin, Jin-Fuw Lee, Chieh-yu Lin, Jawahar Pundalik Nayak, Rama Nand Singh
  • Patent number: 7448018
    Abstract: A system and method of employing patterning process statistics to evaluate layouts for intersect area analysis includes applying Optical Proximity Correction (OPC) to the layout, simulating images formed by the mask and applying patterning process variation distributions to influence and determine corrective actions taken to improve and optimize the rules for compliance by the layout. The process variation distributions are mapped to an intersect area distribution by creating a histogram based upon a plurality of processes for an intersect area. The intersect area is analyzed using the histogram to provide ground rule waivers and optimization.
    Type: Grant
    Filed: September 12, 2006
    Date of Patent: November 4, 2008
    Assignee: International Business Machines Corporation
    Inventors: Fook-Luen Heng, Mark Alan Lavin, Jin-Fuw Lee, Chieh-yu Lin, Jawahar Pundalik Nayak, Rama Nand Singh
  • Publication number: 20080066047
    Abstract: A system and method of employing patterning process statistics to evaluate layouts for intersect area analysis includes applying Optical Proximity Correction (OPC) to the layout, simulating images formed by the mask and applying patterning process variation distributions to influence and determine corrective actions taken to improve and optimize the rules for compliance by the layout. The process variation distributions are mapped to an intersect area distribution by creating a histogram based upon a plurality of processes for an intersect area. The intersect area is analyzed using the histogram to provide ground rule waivers and optimization.
    Type: Application
    Filed: September 12, 2006
    Publication date: March 13, 2008
    Inventors: Fook-Luen Heng, Mark Alan Lavin, Jin-Fuw Lee, Chieh-yu Lin, Jawahar Pundalik Nayak, Rama Nand Singh
  • Patent number: 7302671
    Abstract: An integrated circuit (IC) including at least one combinational logic path. The features in the combinational logic path are self compensating for out-of-focus effects. In particular, field effect transistor (FET) gates may be iso-focally spaced such that the gate (critical dimension) may move with changing focus, but the gate length remains the same. Alternately, logic circuits in a path may self-compensate for focus effects on individual circuits.
    Type: Grant
    Filed: April 1, 2005
    Date of Patent: November 27, 2007
    Assignee: International Business Machines Corporation
    Inventors: Fook-Luen Heng, Jin-Fuw Lee, Daniel L. Ostapko
  • Patent number: 7269817
    Abstract: A method and system for layout optimization relative to lithographic process windows which facilitates lithographic constraints to be non-localized in order to impart a capability of printing a given circuit with a process window beyond the process windows which are attainable with conventional simplified design rules. Pursuant to the method and system, lithographic capability and process windows are maximized to satisfy local circuit requirements and in order to achieve a maximally efficient layout.
    Type: Grant
    Filed: February 10, 2004
    Date of Patent: September 11, 2007
    Assignee: International Business Machines Corporation
    Inventors: Fook-Luen Heng, Mark A. Lavin, Jin-Fuw Lee, Daniel L. Ostapko, Alan E. Rosenbluth, Nakgeuon Seong
  • Publication number: 20050189605
    Abstract: An integrated circuit (IC) including at least one combinational logic path. The features in the combinational logic path are self compensating for out-of-focus effects. In particular, field effect transistor (FET) gates may be iso-focally spaced such that the gate (critical dimension) may move with changing focus, but the gate length remains the same. Alternately, logic circuits in a path may self-compensate for focus effects on individual circuits.
    Type: Application
    Filed: April 1, 2005
    Publication date: September 1, 2005
    Inventors: Fook-Luen Heng, Jin-Fuw Lee, Daniel Ostapko
  • Publication number: 20050177810
    Abstract: A novel method and system for layout optimization relative to lithographic process windows which facilitates lithographic constraints to be non-localized in order to impart a capability of printing a given circuit with a process window beyond the process windows which are attainable with conventional simplified design rules.
    Type: Application
    Filed: February 10, 2004
    Publication date: August 11, 2005
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Fook-Luen Heng, Mark Lavin, Jin-Fuw Lee, Daniel Ostapko, Alan Rosenbluth, Nakgeuon Seong