Abstract: A semiconductor memory device with a capacitor-over-bitline (COB) structure and a method for fabricating the same. The semiconductor memory device includes a transistor having a gate electrode formed on a gate insulating layer on a semiconductor substrate and having source and drain regions formed on the surface of the substrate and separated from each other by the gate electrode, a first interlayer insulating layer formed over the substrate including the transistor; a bitline formed over the first interlayer insulating layer; and a second interlayer insulating layer formed over the substrate including the bitline, for insulating the bitline from a storage node of a capacitor. A surface of the second interlayer insulating layer is planarized by a chemical-mechanical polishing (CMP) process so as to be substantially parallel to a surface of the substrate including the bitline.

Abstract: Methods of forming metal silicide layers include the steps of forming electrically conductive lines that comprise the steps of forming a layer of polysilicon on a semiconductor substrate and then forming a layer of metal silicide on the polysilicon layer, opposite the substrate. The layer of metal silicide and the layer of polysilicon are then patterned as an electrically conductive line having sidewalls. The semiconductor substrate is then exposed to a cleaning agent that selectively etches the patterned layer of metal silicide at a faster rate than the patterned layer of polysilicon. The patterned layer of metal silicide is then thermally oxidized to define recess spacers extending adjacent sidewalls of the electrically conductive line. An electrically insulating layer is then formed on the electrically conductive line and on the recess spacers. The electrically insulating layer is then anisotropically etched to define insulating spacers on the recess spacers.

Abstract: A semiconductor memory device with a capacitor-over-bitline (COB) structure and a method for fabricating the same. The semiconductor memory device includes a transistor having a gate electrode formed on a gate insulating layer on a semiconductor substrate and having source and drain regions formed on the surface of the substrate and separated from each other by the gate electrode, a first interlayer insulating layer formed over the substrate including the transistor; a bitline formed over the first interlayer insulating layer; and a second interlayer insulating layer formed over the substrate including the bitline, for insulating the bitline from a storage node of a capacitor. A surface of the second interlayer insulating layer is planarized by a chemical-mechanical polishing (CMP) process so as to be substantially parallel to a surface of the substrate including the bitline.

Abstract: An integrated circuit is fabricated by forming first source and drain regions and contact regions which electrically contact respective first source and drain regions, for first field effect transistors in an integrated circuit. Then, second source and drain regions for second field effect transistors in the integrated circuit are formed. By simultaneously forming landing pads which electrically contact the integrated circuit substrate between first spaced apart gates, and doping the integrated circuit substrate which electrically contacts the landing pads, an additional protective layer may not be needed, thereby simplifying the fabrication process.