Patents by Inventor Jin Ping Liu

Jin Ping Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150364336
    Abstract: A semiconductor structure with mixed n-type and p-type non-planar transistors includes a residual overlapping mask bump on one or more of the dummy gates. A dielectric layer is created over the structure having a top surface above the residual bump, for example, using a blanket deposition and chemical-mechanical underpolish (i.e., stopping before exposing the gate cap). The residual bump is then transformed into a same material as the dielectric, either in its entirety and then removing the combined dielectric, or by removing the dielectric first and partly removing the residual bump, the remainder of which is then transformed and the dielectric removed. In either case, the structure is planarized for further processing.
    Type: Application
    Filed: June 17, 2014
    Publication date: December 17, 2015
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Hong YU, Haigou HUANG, Jin Ping LIU, Huang LIU
  • Publication number: 20150357332
    Abstract: Devices and methods for forming semiconductor devices with FinFETs are provided. One intermediate semiconductor device includes, for instance: a substrate with at least one fin with at least one channel; at least one gate over the channel; at least one hard-mask over the gate; and at least one spacer disposed over the gate and hard-mask. One method includes, for instance: obtaining an intermediate semiconductor device; forming at least one recess into the substrate, the recess including a bottom and at least one sidewall exposing a portion of the at least one fin; depositing a dielectric layer into the at least one recess; removing at least a portion of the dielectric layer to form a barrier dielectric layer; and performing selective epitaxial growth in the at least one recess over the barrier dielectric layer.
    Type: Application
    Filed: August 21, 2015
    Publication date: December 10, 2015
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Jin Ping LIU, Min-hwa CHI
  • Publication number: 20150357292
    Abstract: Methods of facilitating fabrication of defect-free semiconductor structures are provided which include, for instance: providing a dielectric layer, the dielectric layer comprising at least one consumable material; selectively removing a portion of the dielectric layer, wherein the selectively removing consumes, in part, a remaining portion of the at least one consumable material, leaving, within the remaining portion of the dielectric layer, a depleted region; and subjecting the depleted region of the dielectric layer to a treatment process, to restore the depleted region with at least one replacement consumable material, thereby facilitating fabrication of a defect-free semiconductor structure.
    Type: Application
    Filed: July 15, 2015
    Publication date: December 10, 2015
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Hung-Wei LIU, Zhiguo SUN, Huang LIU, Jin Ping LIU
  • Patent number: 9196710
    Abstract: Integrated circuits with relaxed silicon and germanium fins and methods for fabricating such integrated circuits are provided. The method includes a forming a crystalline silicon and germanium composite layer overlying a crystalline silicon substrate, where a composite layer crystal lattice is relaxed. A fin is formed in the composite layer, and a gate is formed overlying the fin. A portion of the fin is removed on opposite sides of the gate to form a drain cavity and a source cavity, and a source and a drain are formed in the source cavity and drain cavity, respectively.
    Type: Grant
    Filed: February 11, 2014
    Date of Patent: November 24, 2015
    Assignee: GLOBALFOUNDRIES, INC.
    Inventors: Andy Wei, Jin Ping Liu, Shao Ming Koh, Amaury Gendron
  • Publication number: 20150333067
    Abstract: Devices and methods for forming semiconductor devices with FinFETs are provided. One method includes, for instance: obtaining an intermediate semiconductor device with a substrate and at least one shallow trench isolation region; depositing a hard mask layer over the intermediate semiconductor device; etching the hard mask layer to form at least one fin hard mask; and depositing at least one sacrificial gate structure over the at least one fin hard mask and at least a portion of the substrate. One intermediate semiconductor device includes, for instance: a substrate with at least one shallow trench isolation region; at least one fin hard mask over the substrate; at least one sacrificial gate structure over the at least one fin hard mask; at least one spacer disposed on the at least one sacrificial gate structure; and at least one pFET region and at least one nFET region grown into the substrate.
    Type: Application
    Filed: July 29, 2015
    Publication date: November 19, 2015
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Jing WAN, Andy WEI, Lun ZHAO, Dae Geun YANG, Jin Ping LIU, Tien-Ying LUO, Guillaume BOUCHE, Mariappan HARIHARAPUTHIRAN, Churamani GAIRE
  • Publication number: 20150325681
    Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, a method is provided for fabricating an integrated circuit. The method includes forming a first FET trench in a first FET region and a second FET trench in a second FET region of an interlayer dielectric material on a semiconductor substrate, at least partially filling the first and second FET trenches with a work function metal to form a work function metal layer, and at least partially removing a portion of the work function metal layer in the second FET trench. The first FET trench is defined as an NFET trench and the second FET trench is defined as a PFET trench.
    Type: Application
    Filed: May 6, 2014
    Publication date: November 12, 2015
    Inventors: Bongki Lee, Jin Ping Liu, Bharat Krishnan
  • Publication number: 20150295047
    Abstract: A defect-free, relaxed semiconductor covering layer (e.g., epitaxial SiGe) over a semiconductor substrate (e.g., Si) is provided having a strain relaxation degree above about 80% and a non-zero threading dislocation density of less than about 100/cm2. A lattice mismatch exists between the substrate and the covering layer. The covering layer also has a non-zero thickness that may be less than about 0.5 microns. The strain relaxation degree and threading dislocation are achieved by exposing defects at or near a surface of an initial semiconductor layer on the substrate (i.e., exposing defects via selective etch and filling-in any voids created), planarizing the filled-in surface, and creating the covering layer (e.g., growing epitaxy) on the planarized, filled-in surface, which is also planarized.
    Type: Application
    Filed: April 14, 2014
    Publication date: October 15, 2015
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Haigou HUANG, Huang LIU, Jin Ping LIU
  • Publication number: 20150287824
    Abstract: Integrated circuits with stressed semiconductor substrates, processes for preparing stressed semiconductor substrates, and processes for preparing integrated circuits including stressed semiconductor substrates are provided herein.
    Type: Application
    Filed: April 3, 2014
    Publication date: October 8, 2015
    Applicant: GLOBALFOUNDRIES, Inc.
    Inventors: Shishir Ray, Jin Ping Liu, Bharat Krishnan
  • Patent number: 9147696
    Abstract: Devices and methods for forming semiconductor devices with FinFETs are provided. One method includes, for instance: obtaining an intermediate semiconductor device with a substrate and at least one shallow trench isolation region; depositing a hard mask layer over the intermediate semiconductor device; etching the hard mask layer to form at least one fin hard mask; and depositing at least one sacrificial gate structure over the at least one fin hard mask and at least a portion of the substrate. One intermediate semiconductor device includes, for instance: a substrate with at least one shallow trench isolation region; at least one fin hard mask over the substrate; at least one sacrificial gate structure over the at least one fin hard mask; at least one spacer disposed on the at least one sacrificial gate structure; and at least one pFET region and at least one nFET region grown into the substrate.
    Type: Grant
    Filed: October 1, 2013
    Date of Patent: September 29, 2015
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Jing Wan, Andy Wei, Lun Zhao, Dae Geun Yang, Jin Ping Liu, Tien-Ying Luo, Guillaume Bouche, Mariappan Hariharaputhiran, Churamani Gaire
  • Patent number: 9142673
    Abstract: Devices and methods for forming semiconductor devices with FinFETs are provided. One intermediate semiconductor device includes, for instance: a substrate with at least one fin with at least one channel; at least one gate over the channel; at least one hard-mask over the gate; and at least one spacer disposed over the gate and hard-mask. One method includes, for instance: obtaining an intermediate semiconductor device; forming at least one recess into the substrate, the recess including a bottom and at least one sidewall exposing a portion of the at least one fin; depositing a dielectric layer into the at least one recess; removing at least a portion of the dielectric layer to form a barrier dielectric layer; and performing selective epitaxial growth in the at least one recess over the barrier dielectric layer.
    Type: Grant
    Filed: July 31, 2013
    Date of Patent: September 22, 2015
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Jin Ping Liu, Min-hwa Chi
  • Patent number: 9142422
    Abstract: Methods of facilitating fabrication of defect-free semiconductor structures are provided which include, for instance: providing a dielectric layer, the dielectric layer comprising at least one consumable material; selectively removing a portion of the dielectric layer, wherein the selectively removing consumes, in part, a remaining portion of the at least one consumable material, leaving, within the remaining portion of the dielectric layer, a depleted region; and subjecting the depleted region of the dielectric layer to a treatment process, to restore the depleted region with at least one replacement consumable material, thereby facilitating fabrication of a defect-free semiconductor structure.
    Type: Grant
    Filed: November 4, 2013
    Date of Patent: September 22, 2015
    Assignee: GLOBALFOUNDRIES INC
    Inventors: Hung-Wei Liu, Zhiguo Sun, Huang Liu, Jin Ping Liu
  • Patent number: 9142640
    Abstract: A non-planar transistor is fabricated with dummy or sacrificial epitaxy and a structure for subsequent replacement or final epitaxy containment is created around the sacrificial epitaxy. The dummy epitaxy is then removed and replaced with the replacement epitaxy. The containment structure allows for uniform growth of the replacement epitaxy and prevents merger. Where n-type and p-type structures are present, the replacement epitaxy process is performed for each type, while protecting the other type with a mask. Optionally, one of the replacement epitaxies, i.e., the one for n-type or p-type, may be used as the dummy epitaxy, resulting in the need for only one mask.
    Type: Grant
    Filed: June 17, 2014
    Date of Patent: September 22, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Xusheng Wu, Xiaodong Yang, Yanxiang Liu, Jin Ping Liu
  • Publication number: 20150255277
    Abstract: Fin-type transistor fabrication methods and structures are provided having one or more nitrided conformal layers, to improve reliability of the semiconductor device. The method includes, for example, providing at least one material layer disposed, in part, conformally over a fin extending above a substrate, the material layer(s) including a gate dielectric layer; and performing a conformal nitridation process over an exposed surface of the material layer(s), the conformal nitridation process forming an exposed, conformal nitrided surface.
    Type: Application
    Filed: March 7, 2014
    Publication date: September 10, 2015
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Wei Hua TONG, Tien-Ying LUO, Yan Ping SHEN, Feng ZHOU, Jun LIAN, Haoran SHI, Min-hwa CHI, Jin Ping LIU, Haiting WANG, Seung KIM
  • Patent number: 9129987
    Abstract: A method includes providing a gate structure having a gate, a first spacer along at least one side of the gate and an interlayer dielectric on at least one of the gate and the first spacer. The interlayer dielectric is removed to reveal the first spacer. The first spacer is removed and a second spacer is deposited on at least one side of the gate. The second spacer is formed of material having a lower dielectric constant than the first spacer.
    Type: Grant
    Filed: January 24, 2014
    Date of Patent: September 8, 2015
    Assignee: GLOBAL FOUNDRIES, Inc.
    Inventors: Jing Wan, Jin Ping Liu, Guillaume Bouche, Andy Wei, Lakshmanan H. Vanamurthy, Cuiqin Xu, Sridhar Kuchibhatla, Rama Kambhampati, Xiuyu Cai
  • Publication number: 20150243563
    Abstract: In one aspect there is set forth herein an integrated circuit having a first plurality of field effect transistors and a second plurality of field effect transistor, wherein field effect transistors of the first plurality of field effect transistors each have a first gate stack and wherein field effect transistors of the second plurality of field effect transistors each have a second gate stack, the second gate stack being different from the first gate stack by having a metal layer common to the first gate stack and the second gate stack that includes a first thickness at the first gate stack and a second thickness at the second gate stack.
    Type: Application
    Filed: February 25, 2014
    Publication date: August 27, 2015
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Bongki LEE, Jin Ping LIU, Manoj JOSHI, Manfred ELLER, Rohit PAL, Richard J. CARTER, Srikanth Balaji SAMAVEDAM
  • Publication number: 20150243652
    Abstract: In one aspect there is set forth herein a semiconductor device having a first field effect transistor formed in a substrate structure, and a second field effect transistor formed in the substrate structure. The first field effect transistor can include a first substrate structure doping, a first gate stack, and a first threshold voltage. The second field effect transistor can include the first substrate structure doping, a second gate stack different from the first gate stack, and a second threshold voltage different from the first threshold voltage.
    Type: Application
    Filed: February 25, 2014
    Publication date: August 27, 2015
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Manoj JOSHI, Manfred ELLER, Rohit PAL, Richard J. CARTER, Srikanth Balaji SAMAVEDAM, Bongki LEE, Jin Ping LIU
  • Publication number: 20150228755
    Abstract: Integrated circuits with relaxed silicon and germanium fins and methods for fabricating such integrated circuits are provided. The method includes a forming a crystalline silicon and germanium composite layer overlying a crystalline silicon substrate, where a composite layer crystal lattice is relaxed. A fin is formed in the composite layer, and a gate is formed overlying the fin. A portion of the fin is removed on opposite sides of the gate to form a drain cavity and a source cavity, and a source and a drain are formed in the source cavity and drain cavity, respectively.
    Type: Application
    Filed: February 11, 2014
    Publication date: August 13, 2015
    Applicant: GLOBALFOUNDRIES, Inc.
    Inventors: Andy Wei, Jin Ping Liu, Shao Ming Koh, Amaury Gendron
  • Publication number: 20150214330
    Abstract: A method includes providing a gate structure having a gate, a first spacer along at least one side of the gate and an interlayer dielectric on at least one of the gate and the first spacer. The interlayer dielectric is removed to reveal the first spacer. The first spacer is removed and a second spacer is deposited on at least one side of the gate. The second spacer is formed of material having a lower dielectric constant than the first spacer.
    Type: Application
    Filed: January 24, 2014
    Publication date: July 30, 2015
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Jing WAN, Jin Ping LIU, Guillaume BOUCHE, Andy WEI, Lakshmanan H. VANAMURTHY, Cuiqin XU, Sridhar KUCHIBHATLA, Rama KAMBHAMPATI, Xiuyu CAI
  • Patent number: 9087870
    Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes etching an enhanced high-aspect-ratio process (eHARP) oxide fill that is disposed in an STI trench between two adjacent fins to form a recessed eHARP oxide fill. The two adjacent fins extend from a bulk semiconductor substrate. A silicon layer is formed overlying the recessed eHARP oxide fill. The silicon layer is converted to a thermal oxide layer to further fill the STI trench with oxide material.
    Type: Grant
    Filed: May 29, 2013
    Date of Patent: July 21, 2015
    Assignee: GLOBALFOUNDRIES, INC.
    Inventors: Wei Hua Tong, Huang Liu, HongLiang Shen, Jin Ping Liu, Seung Kim
  • Publication number: 20150194307
    Abstract: Methods for fabricating a strained fin structure are provided which include: providing a virtual substrate material over a substrate structure, the virtual substrate material having a virtual substrate lattice constant and a virtual substrate lattice structure; providing a first material over a region of the virtual substrate material, the first material acquiring a strained first material lattice structure by, in part, conforming to the virtual substrate lattice structure; and etching a first fin pattern into the first material. The method may include providing a second material over a second region of the virtual substrate material, the second material acquiring a strained lattice structure by, in part, conforming to the virtual substrate lattice structure, and etching a fin pattern into the second material. The resultant device may have tensile strained fin structures or compressively strained fin structures, or both.
    Type: Application
    Filed: January 6, 2014
    Publication date: July 9, 2015
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Churamani GAIRE, Bharat KRISHNAN, Jin Ping LIU