Abstract: Disclosed is a terminating resistance setting circuit and a battery management system in a battery system including a plurality of battery modules, the battery management system including at least module controllers that respectively control the plurality of battery modules, in which the module controllers communicate with each other through a differential input mode, and each of a plurality of battery modules includes a terminating resistance setting circuit including a resistance generation unit connected between a pair of communication lines for differential input to generate a terminating resistance, a first control circuit that applies a first control signal to the resistance generation unit, and a second control circuit formed between the resistance generation unit and a reference potential and controlled to apply a voltage according to the reference potential to the resistance generation unit by a second control signal.

Abstract: Disclosed is a device and method for monitoring a common mode voltage. There is provided the device for monitoring a common mode voltage including an input end connected to a node between an energy storage device and a power conversion device, a voltage divider that divides a voltage applied to the input end, a comparator that compares an output of the voltage divider and a reference voltage, and a controller that detects an abnormality in a voltage applied from the power conversion device to the energy storage device based on an output of the comparator.

Abstract: A memory module includes a plurality of semiconductor memory devices associated with a same module board. The plurality of semiconductor memory devices configured to simultaneously perform a training operation, the plurality of semiconductor memory devices including a reception interface circuit configured to perform the training operation to search for selected equalization coefficients of an equalizer based on a training pattern from a memory controller, and transmit a training information signal to the memory controller in a training mode in response to a training command from the memory controller, the training information signal including the selected equalization coefficients.

Abstract: A memory module includes a plurality of semiconductor memory devices associated with a same module board. The plurality of semiconductor memory devices configured to simultaneously perform a training operation, the plurality of semiconductor memory devices including a reception interface circuit configured to perform the training operation to search for selected equalization coefficients of an equalizer based on a training pattern from a memory controller, and transmit a training information signal to the memory controller in a training mode in response to a training command from the memory controller, the training information signal including the selected equalization coefficients.

Abstract: The present disclosure relates to a method for preventing duplicate allocation of an ID to battery modules, and in particularly, to a method for preventing duplicate allocation of an ID to battery modules wherein an ID is prevented from being allocated in a duplicated manner by diagnosing each state where the ID is to be allocated in a duplicated manner.

Abstract: A memory module includes a plurality of semiconductor memory devices associated with a same module board. The plurality of semiconductor memory devices configured to simultaneously perform a training operation, the plurality of semiconductor memory devices including a reception interface circuit configured to perform the training operation to search for selected equalization coefficients of an equalizer based on a training pattern from a memory controller, and transmit a training information signal to the memory controller in a training mode in response to a training command from the memory controller, the training information signal including the selected equalization coefficients.

Abstract: A memory device determines an operation mode based on an external voltage. The memory device includes a cell array including a plurality of memory cells; and a mode selector that detects a level of at least one voltage signal externally provided and selects any one of a plurality of operation modes corresponding to a plurality of standards according to a result of detecting the level of the at least one voltage signal. The memory device further includes a mode controller that, in response to a mode selecting signal from the mode selector, outputs setting information for setting the memory device to communicate with a memory controller via an interface according to a selected standard from among the plurality of standards; and a calibrating circuit that generates a control code for controlling circuit blocks in the memory device according to the setting information.

Abstract: A memory device includes a plurality of receivers that each include a first input terminal coupled to one pin of a plurality of input/output pins. The memory devices further includes a transmitter having an output terminal coupled to the first input terminals of the plurality of receivers. The memory device further includes a control circuit configured to control the transmitter to output a particular test signal. The plurality of receivers are each configured to generate output data based on receiving the particular test signal from the transmitter. The control circuit is further configured to adjust the plurality of receivers based on the output data generated by the plurality of receivers and received at the control circuit from the plurality of receivers.

Abstract: A memory device determines an operation mode based on an external voltage. The memory device includes a cell array including a plurality of memory cells; and a mode selector that detects a level of at least one voltage signal externally provided and selects any one of a plurality of operation modes corresponding to a plurality of standards according to a result of detecting the level of the at least one voltage signal. The memory device further includes a mode controller that, in response to a mode selecting signal from the mode selector, outputs setting information for setting the memory device to communicate with a memory controller via an interface according to a selected standard from among the plurality of standards; and a calibrating circuit that generates a control code for controlling circuit blocks in the memory device according to the setting information.

Abstract: The present invention relates to a method of automatically setting a communication resistance of an energy storage device (ESS), and more particularly, to a method of automatically controlling connection of a battery module and a terminating resistance by using a battery management system (BMS) ID allocated to each battery module constituting the ESS.

Abstract: A memory device includes a plurality of receivers that each include a first input terminal coupled to one pin of a plurality of input/output pins. The memory devices further includes a transmitter having an output terminal coupled to the first input terminals of the plurality of receivers. The memory device further includes a control circuit configured to control the transmitter to output a particular test signal. The plurality of receivers are each configured to generate output data based on receiving the particular test signal from the transmitter. The control circuit is further configured to adjust the plurality of receivers based on the output data generated by the plurality of receivers and received at the control circuit from the plurality of receivers.

Abstract: The present invention provides a device and method for waking up an MCU of a BMS operating in a sleep mode. More specifically, the present invention provides a device and method for waking up an MCU of a BMS that is in a sleep mode automatically by generating a wake-up signal only once, when an external power source is connected, without user's operation.

Abstract: A memory module includes a plurality of semiconductor memory devices associated with a same module board. The plurality of semiconductor memory devices configured to simultaneously perform a training operation, the plurality of semiconductor memory devices including a reception interface circuit configured to perform the training operation to search for selected equalization coefficients of an equalizer based on a training pattern from a memory controller, and transmit a training information signal to the memory controller in a training mode in response to a training command from the memory controller, the training information signal including the selected equalization coefficients.

Abstract: A data alignment circuit of a semiconductor memory device including: a data sampling circuit configured to receive a data sequence and an internal data strobe signal, wherein the data sampling circuit samples the data sequence based on the internal data strobe signal to generate first and second data sequences; a division circuit configured to receive a clock signal and the internal data strobe signal, divide the clock signal to produce a divided clock signal and output an alignment control signal by sampling the divided clock signal based on the internal data strobe signal; and a data alignment block configured to receive the first and second data sequences, and the alignment control signal, and align the first and second data sequences in parallel to output internal data.

Abstract: The present disclosure relates to a method for preventing duplicate allocation of an ID to battery modules, and in particularly, to a method for preventing duplicate allocation of an ID to battery modules wherein an ID is prevented from being allocated in a duplicated manner by diagnosing each state where the ID is to be allocated in a duplicated manner.

Abstract: The present invention relates to a method of automatically setting a communication resistance of an energy storage device (ESS), and more particularly, to a method of automatically controlling connection of a battery module and a terminating resistance by using a battery management system (BMS) ID allocated to each battery module constituting the ESS.

Abstract: The present invention provides a device and method for waking up an MCU of a BMS operating in a sleep mode. More specifically, the present invention provides a device and method for waking up an MCU of a BMS that is in a sleep mode automatically by generating a wake-up signal only once, when an external power source is connected, without user's operation.

Abstract: Provided is an apparatus for battery diagnosis and module state change device capable of receiving power from a battery module through a connector connection with a battery module and operating, changing a diagnosis reference value for diagnosing, by a battery management system (BMS), a battery, and changing a setting value of the BMS to change a use of the battery module.

Abstract: A data alignment circuit of a semiconductor memory device including: a data sampling circuit configured to receive a data sequence and an internal data strobe signal, wherein the data sampling circuit samples the data sequence based on the internal data strobe signal to generate first and second data sequences; a division circuit configured to receive a clock signal and the internal data strobe signal, divide the clock signal to produce a divided clock signal and output an alignment control signal by sampling the divided clock signal based on the internal data strobe signal; and a data alignment block configured to receive the first and second data sequences, and the alignment control signal, and align the first and second data sequences in parallel to output internal data.

Abstract: Disclosed is a battery management unit for setting a communication identifier through the frequency of a start signal. The battery management unit according to the present invention analyzes the frequency of a received start signal. If the frequency of the start signal is a fundamental frequency, the battery management unit sets itself as a master unit. If the frequency of the start signal is not the fundamental frequency, the battery management unit sets itself as a slave unit. In addition, when outputting a start signal to another neighboring battery management unit, the battery management unit according to the present invention outputs the start signal by modulating the frequency of the start signal into a frequency produced by adding an additional frequency value to the frequency as received in the battery management unit.