Patents by Inventor Jin-Youn Cho

Jin-Youn Cho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8946796
    Abstract: An image sensor may include at least one device isolation layer that passes through an epitaxial layer in a semiconductor substrate to isolate pixel regions, a light-receiving element in each pixel region, and a transistor in the active region of the semiconductor substrate partitioned by the device isolation layer.
    Type: Grant
    Filed: January 28, 2013
    Date of Patent: February 3, 2015
    Assignee: Dongbu HiTek Co., Ltd.
    Inventor: Jin Youn Cho
  • Patent number: 8760843
    Abstract: A capacitive device includes a first capacitor including a first wiring layer, a first dielectric film, a first conductive layer, a first insulating layer on the first capacitor, a second capacitor on the first insulating layer including a second conductive layer, a second dielectric film, and a third conductive layer, a second insulating layer on the second capacitor, a second wiring layer on the second insulating layer including first and second connection wires, a first via connecting the first wiring layer to the second conductive layer, a second via connecting the third conductive layer to the second wiring layer, a third via connecting the first connection wire to the first conductive layer, and a fourth via connecting the second connection wire to the first wiring layer.
    Type: Grant
    Filed: July 27, 2012
    Date of Patent: June 24, 2014
    Assignee: Dongbu Hitek Co., Ltd.
    Inventors: Jong Taek Hwang, Han Choon Lee, Oh Jin Jung, Jin Youn Cho
  • Publication number: 20130314838
    Abstract: A capacitive device includes a first capacitor including a first wiring layer, a first dielectric film, a first conductive layer, a first insulating layer on the first capacitor, a second capacitor on the first insulating layer including a second conductive layer, a second dielectric film, and a third conductive layer, a second insulating layer on the second capacitor, a second wiring layer on the second insulating layer including first and second connection wires, a first via connecting the first wiring layer to the second conductive layer, a second via connecting the third conductive layer to the second wiring layer, a third via connecting the first connection wire to the first conductive layer, and a fourth via connecting the second connection wire to the first wiring layer.
    Type: Application
    Filed: July 27, 2012
    Publication date: November 28, 2013
    Inventors: Jong Taek HWANG, Han Choon Lee, Oh Jin Jung, Jin Youn Cho
  • Publication number: 20130299935
    Abstract: A method for manufacturing an image sensor may include at least one of the following steps. Forming at least one device isolation layer that passes through an epitaxial layer in a semiconductor substrate to isolate pixel regions. Forming a light-receiving element in each pixel region. The method may include forming a transistor in the active region of the semiconductor substrate partitioned by the device isolation layer.
    Type: Application
    Filed: January 28, 2013
    Publication date: November 14, 2013
    Applicant: Dongbu HiTek Co., Ltd.
    Inventor: Jin Youn CHO
  • Patent number: 8530323
    Abstract: A method for fabricating a capacitor is provided. The method for fabricating a capacitor includes forming a dielectric layer over a lower electrode on a substrate, forming an upper electrode over the dielectric layer, forming a hard mask over the upper electrode, etching the hard mask to form a hard mask pattern, etching the upper electrode to make the dielectric layer remain on the lower electrode in a predetermined thickness, forming an isolation layer along an upper surface of the remaining dielectric layer and the hard mask pattern, leaving the isolation layer having a shape of a spacer on one sidewall of the hard mask pattern, the upper electrode, and the dielectric layer, and etching the lower electrode to be isolated.
    Type: Grant
    Filed: March 9, 2012
    Date of Patent: September 10, 2013
    Assignee: Magnachip Semiconductor, Ltd.
    Inventors: Jin-Youn Cho, Young-Soo Kang, Jong-Il Kim, Sang-Geun Koo
  • Patent number: 8445991
    Abstract: A semiconductor device and a method of manufacturing the semiconductor device are provided. The semiconductor device includes a lower electrode formed on a substrate, a dielectric layer including an etched dielectric region and an as-grown dielectric region formed on the lower electrode, an upper electrode formed on the as-grown dielectric region, a hardmask formed on the upper electrode, a spacer formed at a side surface of the hardmask and the upper electrode and over a surface of the etched dielectric region, and a buffer insulation layer formed on the hardmask and the spacer.
    Type: Grant
    Filed: January 6, 2011
    Date of Patent: May 21, 2013
    Assignee: Magnachip Semiconductor, Ltd.
    Inventors: Jin-Youn Cho, Young-soo Kang, Sang-Geun Koo
  • Patent number: 8310026
    Abstract: A semiconductor device and a method for fabricating the same are provided. The method includes: forming a contact plug passing through an inter-layer insulation layer; sequentially forming a lower electrode layer, a dielectric layer and an upper electrode layer on the inter-layer insulation layer; patterning the upper electrode layer; patterning the dielectric layer and the lower electrode layer, thereby obtaining a capacitor including an upper electrode, a patterned dielectric layer and a lower electrode; and sequentially forming a first metal interconnection line connected with the contact plug and second metal interconnection lines connected with the capacitor.
    Type: Grant
    Filed: January 20, 2010
    Date of Patent: November 13, 2012
    Assignee: Magnachip Semiconductor, Ltd.
    Inventor: Jin-Youn Cho
  • Publication number: 20120171840
    Abstract: A method for fabricating a capacitor is provided. The method for fabricating a capacitor includes forming a dielectric layer over a lower electrode on a substrate, forming an upper electrode over the dielectric layer, forming a hard mask over the upper electrode, etching the hard mask to form a hard mask pattern, etching the upper electrode to make the dielectric layer remain on the lower electrode in a predetermined thickness, forming an isolation layer along an upper surface of the remaining dielectric layer and the hard mask pattern, leaving the isolation layer having a shape of a spacer on one sidewall of the hard mask pattern, the upper electrode, and the dielectric layer, and etching the lower electrode to be isolated.
    Type: Application
    Filed: March 9, 2012
    Publication date: July 5, 2012
    Applicant: MAGNACHIP SEMICONDUCTOR, LTD.
    Inventors: Jin-Youn Cho, Young-Soo Kang, Jong-Il Kim, Sang-Geun Koo
  • Patent number: 8159046
    Abstract: A capacitor includes a lower electrode; a dielectric layer formed on a predetermined portion of the lower electrode; an upper electrode formed on the dielectric layer; a hard mask pattern formed on the upper electrode; and an isolation layer having a shape of a spacer, formed on one sidewall of the hard mask pattern, the upper electrode, and the dielectric layer.
    Type: Grant
    Filed: October 21, 2009
    Date of Patent: April 17, 2012
    Assignee: Magnachip Semiconductor, Ltd.
    Inventors: Jin-Youn Cho, Young-Soo Kang, Jong-Il Kim, Sang-Geun Koo
  • Patent number: 7970356
    Abstract: A terminal location estimation method in a wireless communication system in which an access point (AP) provides an access service to a plurality of terminals includes defining a plurality of beam spaces around the AP through space multiplexing; scheduling the beam spaces according to a predetermined pattern; simultaneously forming a beam in at least one beam space; and detecting the existence and location of a terminal according to whether a response message in response to the formed beam is received. Accordingly, an AP forms beams in a predetermined scheduling pattern, and each of the terminals detecting the beams registers its location by informing the AP that each of the terminals exists in a relevant beam area, and thus, a location of each of the terminals can be estimated without using a complex DOA algorithm.
    Type: Grant
    Filed: January 12, 2007
    Date of Patent: June 28, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chang-Woo Seo, Jin-Youn Cho, Dong-Jun Lee, Kyung-Hun Jang, Gang-Youl Yu
  • Patent number: 7953030
    Abstract: A method and apparatus controls power consumption of stations having a hierarchical structure when the stations transmit and receive a wireless signal to and from one another on a CSMA/CA wireless LAN. The controlling involves extracting information on frame transmission speed and transmission period information on first and second layers of the hierarchical structure from the wireless signal; determining a power-controlled period for each of the first and second layers based on the extracted information; and reducing the power consumption of the first and second layers by switching a current mode of the first and second layers to a predetermined mode for the power-controlled period if a reception address included in the extracted information is not identical to an address of the station.
    Type: Grant
    Filed: July 27, 2004
    Date of Patent: May 31, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chang-woo Seo, Jin-youn Cho, Kyung-hun Jang, Jin-bong Chang, Hyo-sun Hwang, Sang-hyun Woo
  • Publication number: 20110108951
    Abstract: A semiconductor device and a method of manufacturing the semiconductor device are provided. The semiconductor device includes a lower electrode formed on a substrate, a dielectric layer including an etched dielectric region and an as-grown dielectric region formed on the lower electrode, an upper electrode formed on the as-grown dielectric region, a hardmask formed on the upper electrode, a spacer formed at a side surface of the hardmask and the upper electrode and over a surface of the etched dielectric region, and a buffer insulation layer formed on the hardmask and the spacer.
    Type: Application
    Filed: January 6, 2011
    Publication date: May 12, 2011
    Applicant: MAGNACHIP SEMICONDUCTOR, LTD.
    Inventors: Jin-Youn CHO, Young-Soo Kang, Sang-Geun Koo
  • Publication number: 20100155889
    Abstract: A capacitor includes a lower electrode; a dielectric layer formed on a predetermined portion of the lower electrode; an upper electrode formed on the dielectric layer; a hard mask pattern formed on the upper electrode; and an isolation layer having a shape of a spacer, formed on one sidewall of the hard mask pattern, the upper electrode, and the dielectric layer.
    Type: Application
    Filed: October 21, 2009
    Publication date: June 24, 2010
    Inventors: Jin-Youn CHO, Young-Soo Kang, Jong-Il Kim, Sang-Geun Koo
  • Publication number: 20100117197
    Abstract: A semiconductor device and a method for fabricating the same are provided. The method includes: forming a contact plug passing through an inter-layer insulation layer; sequentially forming a lower electrode layer, a dielectric layer and an upper electrode layer on the inter-layer insulation layer; patterning the upper electrode layer; patterning the dielectric layer and the lower electrode layer, thereby obtaining a capacitor including an upper electrode, a patterned dielectric layer and a lower electrode; and sequentially forming a first metal interconnection line connected with the contact plug and second metal interconnection lines connected with the capacitor.
    Type: Application
    Filed: January 20, 2010
    Publication date: May 13, 2010
    Inventor: Jin-Youn CHO
  • Patent number: 7683415
    Abstract: A semiconductor device and a method for fabricating the same are provided. The method includes: forming a contact plug passing through an inter-layer insulation layer; sequentially forming a lower electrode layer, a dielectric layer and an upper electrode layer on the inter-layer insulation layer; patterning the upper electrode layer; patterning the dielectric layer and the lower electrode layer, thereby obtaining a capacitor including an upper electrode, a patterned dielectric layer and a lower electrode; and sequentially forming a first metal interconnection line connected with the contact plug and second metal interconnection lines connected with the capacitor.
    Type: Grant
    Filed: December 12, 2005
    Date of Patent: March 23, 2010
    Assignee: Magnachip Semiconductor, Ltd.
    Inventor: Jin-Youn Cho
  • Patent number: 7643790
    Abstract: Local communication system in wireless communication system includes a main wireless terminal negotiating with each of the peripheral wireless terminals during a time period for which a frame will be transmitted, generating a schedule map including negotiated time information and a transmission sequence of each of the peripheral wireless terminals, and transmitting the generated schedule map to all peripheral wireless terminals; and the peripheral wireless terminals storing the schedule map received from the main wireless terminal, and performing communication with the main wireless terminal according to the sequence determined in the schedule map for the negotiated time period.
    Type: Grant
    Filed: June 2, 2004
    Date of Patent: January 5, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyung-Hun Jang, Chang-Woo Seo, Jin-Bong Cahng, Jin-Youn Cho, Hyo-Sun Hwang
  • Patent number: 7593375
    Abstract: A Medium Access Control (MAC) apparatus and method for use in a channel overlay network of a wireless access system. The wireless access system, which is based on a multi-carrier, includes a plurality of physical modules for receiving signals from a plurality of terminals, a plurality of MAC (Medium Access Control) modules for processing the signals received via the physical modules while being classified according to predetermined traffic classes, and a controller connected to the MAC modules for integratedly managing the MAC modules. The MAC apparatus includes an additional MAC module used for a control channel and a plurality of MAC modules for supporting various QoS traffic data according to individual classes, thereby improving scheduling complexity in a MAC layer.
    Type: Grant
    Filed: July 29, 2005
    Date of Patent: September 22, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chang-Woo Seo, Kyung-Hun Jang, Jin-Youn Cho, Hyo-Sun Hwang
  • Publication number: 20090232252
    Abstract: Systems and methods may be provided for supporting encoding of digital communications, including space time block encoding (STBC). Example systems and methods may include receiving at least one input bit, wherein the at least one input bit is associated with a mapping on a Gray-coded constellation map, storing the received at least one input bit in one or more memory locations, retrieving the at least one bit from the one or more memory locations, inverting a bit of the at least one bit to generate a conjugate of the at least one bit, and obtaining first coordinates of the conjugate according to the Gray-coded constellation map.
    Type: Application
    Filed: March 14, 2008
    Publication date: September 17, 2009
    Inventors: Dukhyun Kim, Jin-Youn Cho
  • Patent number: 7489668
    Abstract: A method for transmitting data at a high rate in a wireless LAN is provided. A wireless access point requests reliable node information from a wireless terminal having a transfer rate equal to or less than a predetermined transfer rate if data to be transmitted to the terminal occurs. The terminal produces a frame containing information related to reliable nodes that can communicate with the terminal and information of greatest transfer rates between the reliable nodes and the terminal, and transmits the frame to the access point. The access point selects an optimal relay node from the reliable nodes, based on the greatest transfer rates between the reliable nodes and the access point and transfer rates between the reliable nodes and the terminal, and determines if a relay gain exists when using the optimal node. If the relay gain exists, the access point performs relay transmission to the terminal; otherwise, it performs direct transmission to it.
    Type: Grant
    Filed: July 26, 2004
    Date of Patent: February 10, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-Youn Cho, Chang-Woo Seo, Jin-Bong Chang, Kyung-Hun Jang, Hyo-Sun Hwang
  • Patent number: 7403506
    Abstract: A handoff method is provided in a communication network including a plurality of fixed nodes attached to a router connected to at least one external network, and at least one mobile node associated with a current fixed node. The method detects movement of a mobile node; prepares a handoff of the mobile node from a current fixed node to potential fixed nodes upon detecting movement of the mobile node; decides whether to handoff to one of the potential fixed nodes as a target fixed node; and performs the handoff from the current fixed node to the target fixed node. The handoff method enables the mobile station to quickly move its association from one access point to another by minimizing a probe delay which is a primary contributor to handoff delay.
    Type: Grant
    Filed: May 31, 2005
    Date of Patent: July 22, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Choong-Hun Lee, Kyung-Hun Jang, Chang-Woo Seo, Jin-Youn Cho, Hyo-Sun Hwang, Sung-Jea Ko, Chun-Su Park