Abstract: A semiconductor chip includes a first wireless communication circuit, a local oscillator (LO) buffer, and an auxiliary path. The first wireless communication circuit has a signal path, wherein the signal path has a mixer input port and a signal node distinct from the mixer input port. The auxiliary path is used to electrically connect the LO buffer to the signal node of the signal path. The LO buffer is reused for a transmit (TX) function through the auxiliary path.

Abstract: A wireless system includes an active oscillator and a front-end circuit. The active oscillator is used to generate and output a reference clock. The active oscillator includes at least one active component, and does not include an electromechanical resonator. The front-end circuit is used to process a transmit (TX) signal or a receive (RX) signal according to a local oscillator (LO) signal. The LO signal is derived from the reference clock.

Abstract: A semiconductor chip includes a first wireless communication circuit, a second wireless communication circuit, and an auxiliary path. The first wireless communication circuit includes a signal path, wherein the signal path includes a signal node. The second wireless communication circuit includes a mixer and a local oscillator (LO) buffer. The LO buffer is arranged to receive and buffer an LO signal, and is further arranged to provide the LO signal to the mixer. The auxiliary path is arranged to electrically connect the LO buffer to the signal node of the signal path, wherein the LO buffer is reused for a loop-back test function of the first wireless communication circuit through the auxiliary path.

Abstract: A semiconductor chip includes a first wireless communication circuit, a local oscillator (LO) buffer, and an auxiliary path. The first wireless communication circuit has a signal path, wherein the signal path has a mixer input port and a signal node distinct from the mixer input port. The auxiliary path is used to electrically connect the LO buffer to the signal node of the signal path. The LO buffer is reused for a loop-back test function through the auxiliary path.

Abstract: A semiconductor chip includes a first wireless communication circuit, a local oscillator (LO) buffer, and an auxiliary path. The first wireless communication circuit has a signal path, wherein the signal path has a mixer input port and a signal node distinct from the mixer input port. The auxiliary path is used to electrically connect the LO buffer to the signal node of the signal path. The LO buffer is reused for a transmit (TX) function through the auxiliary path.

Abstract: A semiconductor chip includes a first wireless communication circuit, a local oscillator (LO) buffer, and an auxiliary path. The first wireless communication circuit has a signal path, wherein the signal path has a mixer input port and a signal node distinct from the mixer input port. The auxiliary path is used to electrically connect the LO buffer to the signal node of the signal path. The LO buffer is reused for a loop-back test function through the auxiliary path.

Abstract: A wireless system includes an active oscillator and a front-end circuit. The active oscillator is used to generate and output a reference clock. The active oscillator includes at least one active component, and does not include an electromechanical resonator. The front-end circuit is used to process a transmit (TX) signal or a receive (RX) signal according to a local oscillator (LO) signal. The LO signal is derived from the reference clock.

Abstract: A transceiver architecture with combined digital beamforming and analog/hybrid beamforming is proposed. Digital beamforming is used for beam training with reduced overhead (switching time). It is beneficial to estimate all UE's angle of arrival (AoA) at the same time. In addition, the pilot/training signals are transmitted in a narrow band to reduce complexity. Analog/hybrid beamforming is used for data transmission with high directive gain and low complexity. The value of beamforming weights (phase shifter values) in analog domain can be based on the estimation of AoA from beam training. By using digital beamforming for beam training, combined with analog/hybrid beamforming for data transmission, effective beamforming is achieved with reduced overhead, complexity, and cost.

Abstract: The calibration method, performed on a phased array device, wherein the method initiates a test signal and looping back a plurality of channel responses corresponding to the channel elements through the transmission line to a calibration circuit in the phased array device, wherein each of the channel responses is obtained when one of the channel elements is turned on, and the rest of the channel elements are turned off. The method further calculates a characteristic value corresponding to the transmission line based on the obtained channel responses of the channel elements, and adjusts a channel parameter of one of the channel elements based on the characteristic value of the transmission line.

Abstract: A transceiver architecture with combined digital beamforming and analog/hybrid beamforming is proposed. Digital beamforming is used for beam training with reduced overhead (switching time). It is beneficial to estimate all UE's angle of arrival (AoA) at the same time. In addition, the pilot/training signals are transmitted in a narrow band to reduce complexity. Analog/hybrid beamforming is used for data transmission with high directive gain and low complexity. The value of beamforming weights (phase shifter values) in analog domain can be based on the estimation of AoA from beam training. By using digital beamforming for beam training, combined with analog/hybrid beamforming for data transmission, effective beamforming is achieved with reduced overhead, complexity, and cost.

Abstract: A phased-array transceiver includes: a plurality of antennas; a plurality of transceiving elements respectively coupled to the plurality of antennas; a signal processing block; and a first distributed network, coupled between the signal processing block and the transceiving elements, wherein the transceiving elements, the signal processing block, and the first distributed network are configured as a single chip, and a first transceiving path between one of the plurality of transceiving elements and the signal processing block and a second transceiving path between another of the plurality of transceiving elements and the signal processing block share at least partial signal traces of the first distributed network.

Abstract: A transceiver architecture with combined digital beamforming and analog/hybrid beamforming is proposed. Digital beamforming is used for beam training with reduced overhead (switching time). It is beneficial to estimate all UE's angle of arrival (AoA) at the same time. In addition, the pilot/training signals are transmitted in a narrow band to reduce complexity. Analog/hybrid beamforming is used for data transmission with high directive gain and low complexity. The value of beamforming weights (phase shifter values) in analog domain can be based on the estimation of AoA from beam training. By using digital beamforming for beam training, combined with analog/hybrid beamforming for data transmission, effective beamforming is achieved with reduced overhead, complexity, and cost.

Abstract: A transceiver architecture with combined digital beamforming and analog/hybrid beamforming is proposed. Digital beamforming is used for beam training with reduced overhead (switching time). It is beneficial to estimate all UE's angle of arrival (AoA) at the same time. In addition, the pilot/training signals are transmitted in a narrow band to reduce complexity. Analog/hybrid beamforming is used for data transmission with high directive gain and low complexity. The value of beamforming weights (phase shifter values) in analog domain can be based on the estimation of AoA from beam training. By using digital beamforming for beam training, combined with analog/hybrid beamforming for data transmission, effective beamforming is achieved with reduced overhead, complexity, and cost.

Abstract: A phase shifter and related load device are provided. The phase shifter includes a phase shifter core and load devices. The phase shifter core has an input port for receiving an input signal, an output port for outputting an output signal, and connection ports. The load devices are coupled to the connection ports, respectively. At least one of the load devices includes first varactor units each having a first node and a second node, where first nodes of the first varactor units are coupled to a first voltage, second nodes of the first varactor units are respectively coupled to a plurality of second voltages, and the second voltages include at least two voltages different from each other. The phase shifter and related load device are capable of mitigating effects resulted from varactor's non-linear C-V curve.

Abstract: The present invention provides for a solution to reduce locking time with satisfactory performance without the need for significant footprint area for the phase lock loop (PLL) circuits by boosting phase frequency detector (PFD) and charge pump (CP) gains through various circuitry configurations that employ one or more flip-flops, delay elements and advanced circuitry techniques.

Abstract: A phased-array transceiver includes: a plurality of antennas; a plurality of transceiving elements respectively coupled to the plurality of antennas; a signal processing block; and a first distributed network, coupled between the signal processing block and the transceiving elements, wherein the transceiving elements, the signal processing block, and the first distributed network are configured as a single chip, and a first transceiving path between one of the plurality of transceiving elements and the signal processing block and a second transceiving path between another of the plurality of transceiving elements and the signal processing block share at least partial signal traces of the first distributed network.

Abstract: The calibration method, performed on a phased array device, wherein the method initiates a test signal and looping back a plurality of channel responses corresponding to the channel elements through the transmission line to a calibration circuit in the phased array device, wherein each of the channel responses is obtained when one of the channel elements is turned on, and the rest of the channel elements are turned off. The method further calculates a characteristic value corresponding to the transmission line based on the obtained channel responses of the channel elements, and adjusts a channel parameter of one of the channel elements based on the characteristic value of the transmission line.

Abstract: The calibration method, performed on a phased array device including channel elements coupled in parallel by a transmission line, has the steps of: obtaining channel responses corresponding to the channel elements through the transmission line, and each of the channel responses is obtained when one of the channel elements is turned on, and the rest of the channel elements are turned off; calculating a characteristic value corresponding to the transmission line based on the obtained channel responses of the channel elements; and adjusting a channel parameter of one of the channel elements based on the characteristic value of the transmission line.

Abstract: The transceiver has a transmitter, a receiver, and a three-port network. The transmitter is configured to transmit an outgoing RF signal. The receiver is configured to receive an incoming RF signal. The three-port network includes: a transmission line, configured to have a line length less than a quarter of a wavelength of the incoming RF signal; an antenna port, configured to connect to an antenna; a receiver port, configured to connect the receiver to the antenna port; and a transmitter port, configured to connect the transmitter to the antenna port and the receiver port through the transmission line.

Abstract: A phase-arrayed device includes: a signal processing circuit arranged to generate a specific signal; a first phase-arrayed channel arranged to provide a first phase-arrayed signal according to the specific signal; a first conducting path arranged to conduct the specific signal to the first phase-arrayed channel; a second conducting path arranged to conduct the first phase-arrayed signal to the signal processing circuit; and a detecting circuit, arranged to detect a mismatch between the first phase-arrayed signal and a reference signal to generate a detecting signal utilized for calibrating the first phase-arrayed signal.