Patents by Inventor Jing-Yao Chang
Jing-Yao Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11756858Abstract: A power module including a main housing, a power element, and at least one assembling component is provided. The main housing has at least one side wall and at least two ribs extending from the side wall. The power element is disposed in the main housing and is closely pressed against a heat dissipation structure by the side wall. The assembling component includes a main section and two bending sections. The main section is located between the two ribs and includes a central portion, at least one movable component, and a peripheral portion. The central portion has a fastening portion, the peripheral portion surrounds the central portion, and the movable component is connected between the central portion and the peripheral portion. The two bending sections are respectively connected to two opposite sides of the peripheral portion and are respectively embedded in the two ribs.Type: GrantFiled: January 4, 2021Date of Patent: September 12, 2023Assignees: Industrial Technology Research Institute, DIODES TAIWAN S.A R.L.Inventors: Wei-Kuo Han, Chia-Yen Lee, Jing-Yao Chang, Tao-Chih Chang
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Publication number: 20230197578Abstract: A power semiconductor device, including a terminal base, is provided. The terminal base has a first end and a second end opposite to each other. The first end has a first flange expanding outward. The first flange is welded to a pad of a substrate by a solder. An included angle between an extension direction of the first flange and a length direction of the terminal base is greater than 90 degrees.Type: ApplicationFiled: February 9, 2022Publication date: June 22, 2023Applicant: Industrial Technology Research InstituteInventors: Tai-Jyun Yu, Sheng-Tsai Wu, Kuo-Shu Kao, Han-Lin Wu, Tai-Kuang Lee, Jing-Yao Chang
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Publication number: 20230138349Abstract: An embedded packaging structure includes a die, a sintered metal layer, an encapsulation layer and a conductive via. The die includes a metallic bonding layer. Sintered metal layer is bonded to the metallic bonding layer. The encapsulation layer covers the die. The conductive via is provided in a blind hole of the encapsulation layer, and the conductive via is electrically connected with the metallic bonding layer through the sintered metal layer.Type: ApplicationFiled: December 27, 2021Publication date: May 4, 2023Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Jing-Yao CHANG, Yu Chih WANG
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Patent number: 11239211Abstract: An electronic device package structure including a substrate, a first circuit layer, a second circuit layer, an electronic device and an input/output device is provided. The first circuit layer includes a first conductive portion, a second conductive portion and a first curve portion located between the first conductive portion and the second conductive portion. At least a partial thickness of the first curve portion is greater than a thickness of the first conductive portion. The electronic device disposed on the second circuit layer is electrically connected to the second conductive portion of the first circuit layer. The input/output device disposed corresponding to the first conductive portion is electrically connected to the first conductive portion of the first circuit layer.Type: GrantFiled: January 7, 2020Date of Patent: February 1, 2022Assignee: Industrial Technology Research InstituteInventors: Wei-Kuo Han, Jing-Yao Chang, Tao-Chih Chang
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Patent number: 11114387Abstract: An electronic package structure is provided. The electronic packaging structure includes a substrate, a conductive layer disposed on the substrate, an intermetallic compound disposed on the conductive layer, a stress buffering material disposed on the substrate and adjacent to the conductive layer, and an electronic device disposed on the conductive layer and the stress buffering material. The intermetallic compound is disposed between the electronic device and the conductive layer, between the electronic device and the stress buffering material, between the substrate and the stress buffering material, and between the conductive layer and the stress buffering material.Type: GrantFiled: August 22, 2018Date of Patent: September 7, 2021Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Jing-Yao Chang, Tao-Chih Chang, Fang-Jun Leu, Wei-Kuo Han, Kuo-Shu Kao
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Publication number: 20210210409Abstract: A power module including a main housing, a power element, and at least one assembling component is provided. The main housing has at least one side wall and at least two ribs extending from the side wall. The power element is disposed in the main housing and is closely pressed against a heat dissipation structure by the side wall. The assembling component includes a main section and two bending sections. The main section is located between the two ribs and includes a central portion, at least one movable component, and a peripheral portion. The central portion has a fastening portion, the peripheral portion surrounds the central portion, and the movable component is connected between the central portion and the peripheral portion. The two bending sections are respectively connected to two opposite sides of the peripheral portion and are respectively embedded in the two ribs.Type: ApplicationFiled: January 4, 2021Publication date: July 8, 2021Applicants: Industrial Technology Research Institute, Lite-On Semiconductor CorporationInventors: Wei-Kuo Han, Chia-Yen Lee, Jing-Yao Chang, Tao-Chih Chang
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Publication number: 20210066257Abstract: An electronic device package structure including a substrate, a first circuit layer, a second circuit layer, an electronic device and an input/output device is provided. The first circuit layer includes a first conductive portion, a second conductive portion and a first curve portion located between the first conductive portion and the second conductive portion. At least a partial thickness of the first curve portion is greater than a thickness of the first conductive portion. The electronic device disposed on the second circuit layer is electrically connected to the second conductive portion of the first circuit layer. The input/output device disposed corresponding to the first conductive portion is electrically connected to the first conductive portion of the first circuit layer.Type: ApplicationFiled: January 7, 2020Publication date: March 4, 2021Applicant: Industrial Technology Research InstituteInventors: Wei-Kuo Han, Jing-Yao Chang, Tao-Chih Chang
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Patent number: 10743411Abstract: A ceramic substrate component suitable for high-power chips includes a ceramic substrate body and at least one raised metal pad. The ceramic substrate body has an upper surface and a lower surface opposite to the upper surface. The raised metal pad includes a base portion and a top layer. The base portion, which is attached to the upper surface of the ceramic substrate body, has a thickness between 10 and 300 micrometers, and a thermal expansion coefficient greater than the ceramic substrate body. The top layer is formed on the base portion and adapted to install a high-power chip thereon. The top layer extends an area less than the base portion but greater than the high-power chip, and has a thermal expansion coefficient greater than the ceramic substrate body. As such, damages due to thermal stress occurring between the base portion and the ceramic substrate body can be mitigated.Type: GrantFiled: January 8, 2020Date of Patent: August 11, 2020Assignees: ICP Technology Co., Ltd., Industrial Technology Research InstituteInventors: Ho-Chieh Yu, Chen-Cheng-Lung Liao, Chun-Yu Lin, Hsiao-Ming Chang, Jing-Yao Chang, Tao-Chih Chang
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Publication number: 20200245456Abstract: A ceramic substrate component suitable for high-power chips includes a ceramic substrate body and at least one raised metal pad. The ceramic substrate body has an upper surface and a lower surface opposite to the upper surface. The raised metal pad includes a base portion and a top layer. The base portion, which is attached to the upper surface of the ceramic substrate body, has a thickness between 10 and 300 micrometers, and a thermal expansion coefficient greater than the ceramic substrate body. The top layer is formed on the base portion and adapted to install a high-power chip thereon. The top layer extends an area less than the base portion but greater than the high-power chip, and has a thermal expansion coefficient greater than the ceramic substrate body. As such, damages due to thermal stress occurring between the base portion and the ceramic substrate body can be mitigated.Type: ApplicationFiled: January 8, 2020Publication date: July 30, 2020Inventors: Ho-Chieh Yu, Chen-Cheng-Lung Liao, Chun-Yu Lin, Hsiao-Ming Chang, Jing-Yao Chang, Tao-Chih Chang
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Patent number: 10672677Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a semiconductor chip, a guard ring, a gel layer, and a first lead frame. The guard ring is disposed on the semiconductor chip, and the gel layer is disposed on the guard ring. The first lead frame is electrically connected to the semiconductor chip, and the gel layer is located between the guard ring and the first lead frame.Type: GrantFiled: May 14, 2018Date of Patent: June 2, 2020Assignees: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE, WIN-HOUSE ELECTRONIC CO., LTD.Inventors: Jing-Yao Chang, Tao-Chih Chang, Kuo-Shu Kao, Fang-Jun Leu, Hsin-Han Lin, Chih-Ming Tzeng, Hsiao-Ming Chang, Chih-Ming Shen
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Patent number: 10490478Abstract: A chip packaging includes a substrate, a first chip, a molding material, a first circuit, and a second circuit. The substrate includes a bottom surface, a first top surface disposed above the bottom surface with a first height, and a second top surface disposed above the bottom surface with a second height. The first height is smaller than the second height. The first chip is disposed on the first top surface. The molding material is disposed on the substrate and covers the first chip. The first and second circuits are disposed on the molding material, and are respectively and electrically connected to the first chip and the second top surface of the substrate. The substrate is made of copper material with huge area and has the properties of high current withstand capacity and high thermal efficiency. The second top surface protects the first chip from damage.Type: GrantFiled: July 12, 2017Date of Patent: November 26, 2019Assignee: Industrial Technology Research InstituteInventors: Yu-Min Lin, Kuo-Shu Kao, Jing-Yao Chang, Tao-Chih Chang
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Publication number: 20180358307Abstract: An electronic package structure is provided. The electronic packaging structure includes a substrate, a conductive layer disposed on the substrate, an intermetallic compound disposed on the conductive layer, a stress buffering material disposed on the substrate and adjacent to the conductive layer, and an electronic device disposed on the conductive layer and the stress buffering material. The intermetallic compound is disposed between the electronic device and the conductive layer, between the electronic device and the stress buffering material, between the substrate and the stress buffering material, and between the conductive layer and the stress buffering material.Type: ApplicationFiled: August 22, 2018Publication date: December 13, 2018Inventors: Jing-Yao Chang, Tao-Chih Chang, Fang-Jun Leu, Wei-Kuo Han, Kuo-Shu Kao
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Publication number: 20180261519Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a semiconductor chip, a guard ring, a gel layer, and a first lead frame. The guard ring is disposed on the semiconductor chip, and the gel layer is disposed on the guard ring. The first lead frame is electrically connected to the semiconductor chip, and the gel layer is located between the guard ring and the first lead frame.Type: ApplicationFiled: May 14, 2018Publication date: September 13, 2018Applicants: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE, Win-House Electronic Co., Ltd.Inventors: Jing-Yao CHANG, Tao-Chih CHANG, Kuo-Shu KAO, Fang-Jun LEU, Hsin-Han LIN, Chih-Ming TZENG, Hsiao-Ming CHANG, Chih-Ming SHEN
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Publication number: 20180233477Abstract: An electronic package structure is provided. The electronic packaging structure includes a substrate, a conductive layer disposed on the substrate, an intermetallic compound disposed on the conductive layer, a stress buffering material and an electronic device. The stress buffering material is disposed on the substrate and adjacent to the conductive layer. The electronic device is disposed on the intermetallic compound and the stress buffering material, and the electronic device is in contact with the intermetallic compound. The stress buffering material is adjacent to the conductive layer to have the conductive layer and the stress buffering material together serving as a stress buffer, so as to enhance the effect of stress buffering, thereby preventing a wafer from cracking due to stress.Type: ApplicationFiled: April 14, 2017Publication date: August 16, 2018Inventors: Jing-Yao Chang, Tao-Chih Chang, Fang-Jun Leu, Wei-Kuo Han, Kuo-Shu Kao
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Publication number: 20180019178Abstract: A chip packaging includes a substrate, a first chip, a molding material, a first circuit, and a second circuit. The substrate includes a bottom surface, a first top surface disposed above the bottom surface with a first height, and a second top surface disposed above the bottom surface with a second height. The first height is smaller than the second height. The first chip is disposed on the first top surface. The molding material is disposed on the substrate and covers the first chip. The first and second circuits are disposed on the molding material, and are respectively and electrically connected to the first chip and the second top surface of the substrate. The substrate is made of copper material with huge area and has the properties of high current withstand capacity and high thermal efficiency. The second top surface protects the first chip from damage.Type: ApplicationFiled: July 12, 2017Publication date: January 18, 2018Applicant: Industrial Technology Research InstituteInventors: Yu-Min Lin, Kuo-Shu Kao, Jing-Yao Chang, Tao-Chih Chang
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Patent number: 9706656Abstract: A signal transmission board includes a substrate, a conductive via, a cavity and a connecting hole. The substrate has a first external surface and a second external surface. The conductive via penetrating through the substrate has a first end and a second end. The first end is disposed on the first external surface, and the second end is disposed on the second external surface. The cavity is disposed in the substrate and penetrated by the conductive via. The connecting hole disposed on the substrate has a third end and a fourth end. The third end is disposed on the first external surface, and the fourth end communicates with the cavity.Type: GrantFiled: November 24, 2015Date of Patent: July 11, 2017Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Chien-Min Hsu, Shih-Hsien Wu, Jing-Yao Chang, Tao-Chih Chang, Ren-Shin Cheng, Min-Lin Lee
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Publication number: 20170084521Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a semiconductor chip, a guard ring, a gel layer, and a first lead frame. The guard ring is disposed on the semiconductor chip, and the gel layer is disposed on the guard ring. The first lead frame is electrically connected to the semiconductor chip, and the gel layer is located between the guard ring and the first lead frame.Type: ApplicationFiled: May 4, 2016Publication date: March 23, 2017Applicants: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE, Win-House Electronic Co.,Ltd.Inventors: Jing-Yao CHANG, Tao-Chih CHANG, Kuo-Shu KAO, Fang-Jun LEU, Hsin-Han LIN, Chih-Ming TZENG, Hsiao-Ming CHANG, Chih-Ming SHEN
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Patent number: 9484315Abstract: A chip structure includes a chip, a first metal layer, a second metal layer and a bonding wire. The first metal layer is disposed on the chip, and a material of the first metal layer includes nickel or nickel alloy. The second metal layer is disposed on the first metal layer, and a material of the second metal layer includes copper, copper alloy, aluminum, aluminum alloy, palladium or palladium alloy. The bonding wire is connected to the second metal layer, and a material of the bonding wire includes copper or copper alloy.Type: GrantFiled: March 26, 2015Date of Patent: November 1, 2016Assignee: Industrial Technology Research InstituteInventors: Yu-Min Lin, Po-Chen Lin, Jing-Yao Chang
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Publication number: 20160174360Abstract: A signal transmission board includes a substrate, a conductive via, a cavity and a connecting hole. The substrate has a first external surface and a second external surface. The conductive via penetrating through the substrate has a first end and a second end. The first end is disposed on the first external surface, and the second end is disposed on the second external surface. The cavity is disposed in the substrate and penetrated by the conductive via. The connecting hole disposed on the substrate has a third end and a fourth end. The third end is disposed on the first external surface, and the fourth end communicates with the cavity.Type: ApplicationFiled: November 24, 2015Publication date: June 16, 2016Inventors: Chien-Min HSU, Shih-Hsien WU, Jing-Yao CHANG, Tao-Chih CHANG, Ren-Shin CHENG, Min-Lin LEE
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Publication number: 20160163665Abstract: A chip structure includes a chip, a first metal layer, a second metal layer and a bonding wire. The first metal layer is disposed on the chip, and a material of the first metal layer includes nickel or nickel alloy. The second metal layer is disposed on the first metal layer, and a material of the second metal layer includes copper, copper alloy, aluminum, aluminum alloy, palladium or palladium alloy. The bonding wire is connected to the second metal layer, and a material of the bonding wire includes copper or copper alloy.Type: ApplicationFiled: March 26, 2015Publication date: June 9, 2016Inventors: Yu-Min Lin, Po-Chen Lin, Jing-Yao Chang