Patents by Inventor Jin-hyun Shin
Jin-hyun Shin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240088469Abstract: A battery module includes a sub module including a cell stack having a plurality of battery cells and a pair of bus bar frames respectively coupled to one side and the other side of the cell stack; a module housing configured to accommodate the sub module and configured to have an air inlet and an air outlet formed to circulate air; a sprinkler provided through the module housing at one side of the cell stack in a stacking direction; and an outlet closing device configured to move by a buoyancy generated by a cooling water introduced into the module housing through the sprinkler so that the air outlet is closed.Type: ApplicationFiled: March 4, 2021Publication date: March 14, 2024Applicant: LG ENERGY SOLUTION, LTD.Inventors: Seung-Hyun KIM, Ji-Won JEONG, Kyung-Hyun BAE, Jin-Kyu SHIN, Jin-Kyu LEE
-
Publication number: 20240072374Abstract: A battery module includes a cell stack in which a plurality of battery cells are vertically stacked; a module housing including a base plate supporting the cell stack and a pair of side plates covering both side portions of the cell stack; a bus bar frame assembly covering an opening portion formed on a side of the module housing in a longitudinal direction of the module housing; and a plurality of spark delay portions protruding from an inner surface of each of the pair of side plates and spaced apart from one another in a height direction of the side plate.Type: ApplicationFiled: January 11, 2022Publication date: February 29, 2024Applicant: LG ENERGY SOLUTION, LTD.Inventors: Seung-Hyun KIM, Yu-Dam KONG, Jin-Kyu SHIN, Young-Hoo OH, Seung-Min OK, Sang-Hyun JO, Sung-Goen HONG
-
Publication number: 20240072401Abstract: A battery module ac includes a cell stack in which a plurality of battery cells are vertically stacked; a module housing including a base plate supporting the cell stack, and a pair of side plates covering both side portions of the cell stack and each including a spark direction changing portion formed by bending an end portion of the side plate in a longitudinal direction of the side plate toward the cell stack; and a bus bar frame assembly covering an opening portion formed on a side of the module housing in a longitudinal direction of the module housing, the bus bar frame assembly including a bus bar frame coupled to a side of the cells tack in a longitudinal direction of the cell stack and a bus bar located on the bus bar frame and coupled to an electrode lead of the battery cell.Type: ApplicationFiled: January 11, 2022Publication date: February 29, 2024Applicant: LG ENERGY SOLUTION, LTD.Inventors: Sang-Hyun JO, Yu-Dam KONG, Seung-Hyun KIM, Jin-Kyu SHIN, Young-Hoo OH, Seung-Min OK, Sung-Goen HONG
-
Publication number: 20240072370Abstract: A battery pack includes a sub-pack including a plurality of battery modules that are located adjacent to one another; a duct coupled to a side of the sub-pack in a width direction of the sub-pack; and a duct cover covering a duct opening portion formed on a side of the duct in a longitudinal direction of the duct, the duct cover including a filter having a mesh structure.Type: ApplicationFiled: January 11, 2022Publication date: February 29, 2024Applicant: LG ENERGY SOLUTION, LTD.Inventors: Sang-Hyun JO, Yu-Dam KONG, Seung-Hyun KIM, Jin-Kyu SHIN, Young-Hoo OH, Seung-Min OK, Sung-Goen HONG
-
Publication number: 20240072228Abstract: A display device comprises a first pixel including a first emission area, a second pixel including a second emission area spaced apart from the first emission area in a first direction, and a bank partitioning the first emission area and the second emission area, wherein the first pixel includes a first alignment electrode, a second alignment electrode, and a third alignment electrode sequentially located, spaced apart from each other in the first direction, and overlapping with the first emission area, first light-emitting elements above, and overlapping with, the first alignment electrode and the second alignment electrode, second light-emitting elements above, and overlapping with, the second alignment electrode and the third alignment electrode, and a dummy electrode between the first emission area and the second emission area, and overlapping with the bank.Type: ApplicationFiled: August 2, 2023Publication date: February 29, 2024Inventors: Won Jun LEE, Dong Woo KIM, Do Yeong PARK, Se Hyun LEE, Kwi Hyun KIM, Min Gyeong SHIN, Jin Joo HA
-
Patent number: 10600805Abstract: A vertical memory device includes a substrate, a plurality of channels on the substrate and extending in a first direction that vertical to a top surface of the substrate, a plurality of gate lines and a conductive line on the substrate. The gate lines are stacked on top of each other. The gate lines surround the channels. The gate lines are spaced apart from each other along the first direction. The conductive line cuts the gate lines along the first direction. A width of the conductive line is periodically and repeatedly changed.Type: GrantFiled: October 11, 2018Date of Patent: March 24, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Joo-Hee Park, Jong-Min Lee, Seon-Kyung Kim, Kee-Jeong Rho, Jin-hyun Shin, Jong-Hyun Park, Jin-Yeon Won
-
Publication number: 20190043889Abstract: A vertical memory device includes a substrate, a plurality of channels on the substrate and extending in a first direction that vertical to a top surface of the substrate, a plurality of gate lines and a conductive line on the substrate. The gate lines are stacked on top of each other. The gate lines surround the channels. The gate lines are spaced apart from each other along the first direction. The conductive line cuts the gate lines along the first direction. A width of the conductive line is periodically and repeatedly changed.Type: ApplicationFiled: October 11, 2018Publication date: February 7, 2019Applicant: Samsung Electronics Co., Ltd.Inventors: Joo-Hee PARK, Jong-Min LEE, Seon-Kyung KIM, Kee-Jeong RHO, Jin-hyun SHIN, Jong-Hyun PARK, Jin-Yeon WON
-
Publication number: 20170104000Abstract: A vertical memory device includes a substrate, a plurality of channels on the substrate and extending in a first direction that vertical to a top surface of the substrate, a plurality of gate lines and a conductive line on the substrate. The gate lines are stacked on top of each other. The gate lines surround the channels. The gate lines are spaced apart from each other along the first direction. The conductive line cuts the gate lines along the first direction. A width of the conductive line is periodically and repeatedly changed.Type: ApplicationFiled: October 12, 2016Publication date: April 13, 2017Inventors: Joo-Hee PARK, Jong-Min LEE, Seon-Kyung KIM, Kee-Jeong RHO, Jin-hyun SHIN, Jong-Hyun PARK, Jin-Yeon WON
-
Patent number: 9525065Abstract: Semiconductor devices are provided. A semiconductor device includes a stack of gate electrodes. The semiconductor device includes a channel material in a channel recess in the stack. The semiconductor device includes a channel pad on the channel insulating layer. The channel pad has a curved upper surface. Methods of manufacturing semiconductor devices are also provided.Type: GrantFiled: December 22, 2015Date of Patent: December 20, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Dong Min Kyeon, Woong Seop Lee, Jin Hyun Shin
-
Patent number: 9379122Abstract: A memory device includes an array of floating gate memory cells. Adjacent memory cells are separated by a plurality of air gaps that electrically decouple respective active regions of adjacent memory cells from one another. Additionally, the air gaps electrically decouple an active region of a memory cell from a floating gate of an adjacent memory cell.Type: GrantFiled: January 20, 2015Date of Patent: June 28, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Jin-Hyun Shin, Jae-Bok Baek
-
Patent number: 9330931Abstract: In a method of manufacturing a semiconductor device, which uses a triple patterning process, a porous layer covering sidewalls and an upper surface of a polymer-containing pattern is formed on a layer to be etched. A decomposition gas is supplied to the polymer-containing pattern through the porous layer, and a portion of the polymer-containing pattern is decomposed to form a reduced polymer-containing pattern and form a void between the reduced polymer-containing pattern and the porous layer. A portion of the porous layer is removed to form a porous spacer pattern spaced apart from the reduced polymer-containing pattern. The layer to be etched is etched by using the reduced polymer-containing pattern and the porous spacer pattern as an etch mask.Type: GrantFiled: December 12, 2014Date of Patent: May 3, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Min-sung Song, Jin-hyun Shin, Jae-hwang Sim, Joon-sung Lim, Bong-hyun Choi
-
Publication number: 20150371996Abstract: A memory device includes an array of floating gate memory cells. Adjacent memory cells are separated by a plurality of air gaps that electrically decouple respective active regions of adjacent memory cells from one another. Additionally, the air gaps electrically decouple an active region of a memory cell from a floating gate of an adjacent memory cell.Type: ApplicationFiled: January 20, 2015Publication date: December 24, 2015Inventors: Jin-Hyun Shin, Jae-Bok Baek
-
Publication number: 20150348795Abstract: In a method of manufacturing a semiconductor device, which uses a triple patterning process, a porous layer covering sidewalls and an upper surface of a polymer-containing pattern is formed on a layer to be etched. A decomposition gas is supplied to the polymer-containing pattern through the porous layer, and a portion of the polymer-containing pattern is decomposed to form a reduced polymer-containing pattern and form a void between the reduced polymer-containing pattern and the porous layer. A portion of the porous layer is removed to form a porous spacer pattern spaced apart from the reduced polymer-containing pattern. The layer to be etched is etched by using the reduced polymer-containing pattern and the porous spacer pattern as an etch mask.Type: ApplicationFiled: December 12, 2014Publication date: December 3, 2015Inventors: Min-sung Song, Jin-hyun Shin, Jae-hwang Sim, Joon-sung Lim, Bong-hyun Choi
-
Publication number: 20140138759Abstract: In an integrated circuit device and method of manufacturing the same, a resistor pattern is positioned on a device isolation layer of a substrate. The resistor pattern includes a resistor body positioned in a recess portion of the device isolation layer and a connector making contact with the resistor body and positioned on the device isolation layer around the recess portion. The connector has a metal silicide pattern having electric resistance lower than that of the resistor body at an upper portion. A gate pattern is positioned on the active region of the substrate and includes the metal silicide pattern at an upper portion. A resistor interconnection is provided to make contact with the connector of the resistor pattern. A contact resistance between the connector and the resistor interconnection is reduced.Type: ApplicationFiled: January 8, 2014Publication date: May 22, 2014Applicant: SAMSUNG Electronics Co., Ltd.Inventors: Young-Ho LEE, Keon-Soo KIM, Seong-Soon CHO, Jin- Hyun SHIN
-
Patent number: 8642438Abstract: In an integrated circuit device and method of manufacturing the same, a resistor pattern is positioned on a device isolation layer of a substrate. The resistor pattern includes a resistor body positioned in a recess portion of the device isolation layer and a connector making contact with the resistor body and positioned on the device isolation layer around the recess portion. The connector has a metal silicide pattern having electric resistance lower than that of the resistor body at an upper portion. A gate pattern is positioned on the active region of the substrate and includes the metal silicide pattern at an upper portion. A resistor interconnection is provided to make contact with the connector of the resistor pattern. A contact resistance between the connector and the resistor interconnection is reduced.Type: GrantFiled: December 13, 2011Date of Patent: February 4, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Young-Ho Lee, Keon-Soo Kim, Seong-Soon Cho, Jin-Hyun Shin
-
Patent number: 8487383Abstract: A flash memory device, including a cell array region where a plurality of memory cells are connected in series to a single cell string, the cell array region including a pocket p-well configured to accommodate the plurality of memory cells and an n-well configured to surround the pocket p-well, a first peripheral region where low-voltage (LV) and high-voltage (HV) switches are connected to the memory cells through a word line, and a second peripheral region where bulk voltage switches are connected to bulk regions of the LV and HV switches.Type: GrantFiled: December 9, 2010Date of Patent: July 16, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Yoon-Moon Park, Se-Jun Park, Suk-Kang Sung, Keon-Soo Kim, Jung-Dal Choi, Choong-Ho Lee, Jin-Hyun Shin, Seung-Wook Choi, Dong-Hoon Jang
-
Publication number: 20120178234Abstract: In an integrated circuit device and method of manufacturing the same, a resistor pattern is positioned on a device isolation layer of a substrate. The resistor pattern includes a resistor body positioned in a recess portion of the device isolation layer and a connector making contact with the resistor body and positioned on the device isolation layer around the recess portion. The connector has a metal silicide pattern having electric resistance lower than that of the resistor body at an upper portion. A gate pattern is positioned on the active region of the substrate and includes the metal silicide pattern at an upper portion. A resistor interconnection is provided to make contact with the connector of the resistor pattern. A contact resistance between the connector and the resistor interconnection is reduced.Type: ApplicationFiled: December 13, 2011Publication date: July 12, 2012Applicant: Samsung Electronics Co., Ltd.Inventors: Young-Ho LEE, Keon-Soo Kim, Seong-Soon Cho, Jin-Hyun Shin
-
Patent number: 8187935Abstract: A method of forming an active region structure includes preparing a semiconductor substrate having a cell array region and a peripheral circuit region, forming upper cell mask patterns having a line shape in the cell array region, forming first and second peripheral mask patterns in the peripheral circuit region, the first and second peripheral mask patterns being stacked in sequence and covering the peripheral circuit region, and upper surfaces of the upper cell mask patterns forming a step difference with an upper surface of the second peripheral mask pattern, forming spacers on sidewalls of the upper cell mask patterns to expose lower portions of the upper cell mask patterns and the second peripheral mask pattern, and removing the lower portions of the upper cell mask patterns using the spacers and the first and second peripheral mask patterns as an etch mask.Type: GrantFiled: June 7, 2010Date of Patent: May 29, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Young-Ho Lee, Keon-Soo Kim, Jae-Hwang Sim, Jin-Hyun Shin, Kyung-Hoon Min
-
Publication number: 20110140202Abstract: A flash memory device, including a cell array region where a plurality of memory cells are connected in series to a single cell string, the cell array region including a pocket p-well configured to accommodate the plurality of memory cells and an n-well configured to surround the pocket p-well, a first peripheral region where low-voltage (LV) and high-voltage (HV) switches are connected to the memory cells through a word line, and a second peripheral region where bulk voltage switches are connected to bulk regions of the LV and HV switches.Type: ApplicationFiled: December 9, 2010Publication date: June 16, 2011Inventors: Yoon-Moon PARK, Se-Jun Park, Suk-Kang Sung, Keon-Soo Kim, Jung-Dal Choi, Choong-Ho Lee, Jin-Hyun Shin, Seung-Wook Choi, Dong-Hoon Jang
-
Publication number: 20110092048Abstract: A method of forming an active region structure includes preparing a semiconductor substrate having a cell array region and a peripheral circuit region, forming upper cell mask patterns having a line shape in the cell array region, forming first and second peripheral mask patterns in the peripheral circuit region, the first and second peripheral mask patterns being stacked in sequence and covering the peripheral circuit region, and upper surfaces of the upper cell mask patterns forming a step difference with an upper surface of the second peripheral mask pattern, forming spacers on sidewalls of the upper cell mask patterns to expose lower portions of the upper cell mask patterns and the second peripheral mask pattern, and removing the lower portions of the upper cell mask patterns using the spacers and the first and second peripheral mask patterns as an etch mask.Type: ApplicationFiled: June 7, 2010Publication date: April 21, 2011Inventors: Young-Ho Lee, Keon-Soo Kim, Jae-Hwang Sim, Jin-Hyun Shin, Kyung-Hoon Min