Abstract: According to one embodiment, an information processing apparatus is allowed to access a storage device storing time-series data generated by a first device. The information processing apparatus includes a processor holding a first public key and a first private key. The processor is configured to acquire a program for correcting an error in first data on a first product from a first entity. The processor is configured to correct the correction target first data, using data in a predetermined range of the time-series data. The processor is configured to generate ground data indicating correction grounds for the corrected correction target first data, based on the data in the predetermined range, and add the ground data to the corrected correction target first data.

Abstract: According to one embodiment, a data protection apparatus includes a processor configured to execute an encryption process on log data including a data frame including a plurality of pieces of data generated along a time sequence. The processor is configured to encrypt each of the pieces of data with a corresponding encryption key among a first initial key and a first encryption keys generated in a forward direction to a time sequence of the pieces of data. The processor is configured to encrypt each of a plurality of pieces of data encrypted with the corresponding encryption key with a corresponding encryption key among a second initial key and a second encryption keys generated in a backward direction to a time sequence of the pieces of data.

Abstract: An entertainment device includes a general-purpose signal processor made up of an assembly of component-processors, each of which can operate in parallel under operating environments independent of others component-processors. A management processor controls a cross bar so as to change the operating environments of the respective component-processors in accordance with a demand for signal processing which is given from a CPU, and to change over any one of the component-processors which receives a signal to be processed which is inputted through the cross bar or outputs a processed signal in accordance with the demand for signal processing.

Abstract: According to one embodiment, a CPU boots a small OS having a function of executing a target application, boots the target application on the booted small OS, and boots a CPU dispatcher for switching an execution OS. The CPU boots a rich OS capable of executing applications larger in number than applications executed by the small OS by using the CPU dispatcher, in a background of the small OS, while causing the target application booted on the small OS to run. After the rich OS is booted, the CPU boots the target application on the booted OS separately from the target application running on the small OS. The CPU passes an execution state of the target application running on the small OS to the target application booted on the rich OS and shifting the execution OS from the small OS to the rich OS.

Abstract: An apparatus of drawing graphics includes an edge coefficient calculator calculating, from vertex data on vertices of a triangle, edge coefficients of edge functions used to determine whether a pixel is present in an inside region of the triangle, and a bounding box calculator calculating a bounding box of projected images of the triangle on a projection plane based on the edge coefficients. The apparatus also includes a starting point determiner and a traverser. The starting point determiner classifies the projected images of the triangle based on a combination of the edge coefficients for respective sides of the triangle, and determines a scan starting point from a corner of the bounding box based on classification of the projected images. The traverser generates pixel data used in rasterization by scanning the bounding box from the scan starting point.

Abstract: An apparatus of drawing graphics includes an edge coefficient calculator calculating, from vertex data on vertices of a triangle, edge coefficients of edge functions used to determine whether a pixel is present in an inside region of the triangle, and a bounding box calculator calculating a bounding box of projected images of the triangle on a projection plane based on the edge coefficients. The apparatus also includes a starting point determiner and a traverser. The starting point determiner classifies the projected images of the triangle based on a combination of the edge coefficients for respective sides of the triangle, and determines a scan starting point from a corner of the bounding box based on classification of the projected images. The traverser generates pixel data used in rasterization by scanning the bounding box from the scan starting point.

Abstract: A video output controller has a video output buffer, a DMA controller, and a display controller. The display controller has a DMA command list processor configured to determine which of the DMA commands contained in the DMA command list must be issued, an initialize signal port configured to receive an initialize signal for starting initialization, a step signal port configured to receive a step signal for starting the issuance of the DMA command, and an external signal processor configured to provide the DMA command list processor with a timing signal for issuing a DMA command according to the initialize signal and step signal .

Abstract: An apparatus of drawing graphics includes an edge coefficient calculator calculating, from vertex data on vertices of a triangle, edge coefficients of edge functions used to determine whether a pixel is present in an inside region of the triangle, and a bounding box calculator calculating a bounding box of projected images of the triangle on a projection plane based on the edge coefficients. The apparatus also includes a starting point determiner and a traverser. The starting point determiner classifies the projected images of the triangle based on a combination of the edge coefficients for respective sides of the triangle, and determines a scan starting point from a corner of the bounding box based on classification of the projected images. The traverser generates pixel data used in rasterization by scanning the bounding box from the scan starting point.

Abstract: A video output controller has a video output buffer, a DMA controller, and a display controller. The display controller has a DMA command list processor configured to determine which of the DMA commands contained in the DMA command list must be issued, an initialize signal port configured to receive an initialize signal for starting initialization, a step signal port configured to receive a step signal for starting the issuance of the DMA command, and an external signal processor configured to provide the DMA command list processor with a timing signal for issuing a DMA command according to the initialize signal and step signal.

Abstract: An entertainment device includes a general-purpose signal processor 103 made up of an assembly of component-processors 103A to 103D each of which can operate in parallel under operating environments independent of others component-processors. A management processor 101 controls a cross bar 104 so as to change the operating environments of the respective component-processors 103A to 103D in accordance with a demand for signal processing which is given from a CPU 11, and to change over any one of the component-processors which receives a signal to be processed which is inputted through the cross bar 104 or outputs a processed signal in accordance with the demand for signal processing.

Abstract: A multiprocessor system according to the present invention, comprises a plurality of calculation processors which execute tasks by using data stored in a memory; and a control processor which controls execution of the tasks by said calculation processors; wherein said control processor includes: a dependency relation checking part which checks a dependency relation between a plurality of data when executing the tasks; and a scheduling part which performs access to said memory, data transfer from said memory to said calculation processor, and calculation scheduling in said calculation processors.

Abstract: A logic simulation system capable of handling a very large scale circuit while realizing a high speed simulation by retaining the parallelism of the simulation targets.