Patents by Inventor Jiro Ohshima

Jiro Ohshima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5382549
    Abstract: In a semiconductor device, the polysilicon resistor or electrode formed of a polysilicon film has a columnar crystalline orientation vertical to the surface of the semiconductor substrate. Thus, the variation in grain size due to the subsequent heat treatment is small, and therefore, the polysilicon resistor or electrode has a high uniformity of resistance value. In addition, since the polysilicon film is formed in the groove in the insulating film formed on the semiconductor substrate, a polysilicon pattern surface which is flush with the surface of the insulating film can be obtained. Thus, unevenness does not occur on the surface of a passivation CVD film coated in the subsequent step, and metal wires formed thereon are not cut.
    Type: Grant
    Filed: July 2, 1993
    Date of Patent: January 17, 1995
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Jiro Ohshima, Toshiyo Motozima
  • Patent number: 5102826
    Abstract: According to the method of manufacturing a semiconductor device of the present invention, an insulation film is formed on a silicon substrate, and a resist film having a predetermined pattern is formed on the insulation film, followed by forming an opening on the insulation film with the resist film performing as a mask. Then, an impurity having conductivity are implanted into said silicon substrate with the resist film performing as a mask and silicon ions are implanted into the silicon substrate with the resist film performing as a mask. After that, the resist film is removed. Further, a refractory metal film which covers at least the opening is formed. Moveover, a diffusion layer which causes electrical activation of the impurity having conductivity is formed by annealing, followed by formation a silicide layer at where the surfaces of the silicon substrate and the metal film meet.
    Type: Grant
    Filed: November 9, 1990
    Date of Patent: April 7, 1992
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Jiro Ohshima, Shin-ichi Taka, Toshiyo Motozima, Hiroshi Naruse
  • Patent number: 4975381
    Abstract: This invention discloses a method of manufacturing an SST bipolar transistor, and the manufacturing method is capable of defining the size of a base region of the SST bipolar transistor. An insulating film and a spacer film serving as a spacer are sequentially formed in a bipolar transistor forming region on the main surface of a semiconductor substrate. Thereafter, the spacer film is patterned into a spacer film pattern for defining the size of the base region. A second insulating film, a base electrode pattern and a third insulating film are sequentially formed on the spacer film pattern. A first opening which reaches the spacer film pattern through the second insulating film, the base electrode pattern and the third insulating film is formed. The spacer film pattern is etched from the first opening to form a second opening having a diameter larger than that of the first opening. The insulating film exposed in the second opening is etched.
    Type: Grant
    Filed: March 12, 1990
    Date of Patent: December 4, 1990
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shin-ichi Taka, Jiro Ohshima
  • Patent number: 4871685
    Abstract: A metal layer is formed by selective CVD method on an emitter region formed by using a field oxide film as a mask. Opening for ion-implanting an impurity for forming external base region is formed in the field oxide film by utilizing the metal layer and a metal layer creep up a bird's beak of the field oxide film as masks. An impurity is doped in a semiconductor substrate through the opening formed in the field oxide film to form external base region. The distance between the emitter region and external base region is controlled by a length of the metal layer creep up the bird's beak.
    Type: Grant
    Filed: August 11, 1988
    Date of Patent: October 3, 1989
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shin-ichi Taka, Jiro Ohshima
  • Patent number: 4853342
    Abstract: A transistor is formed according to the solid phase epitaxial growth which is one of the semiconductor integrated circuit device manufacturing techniques. A low-concentration impurity region is formed by selective solid phase epitaxial growth instead of using an epitaxial substrate. The solid phase epitaxial growth is performed twice, when a collector region is formed and when a base region is formed. The depth of collector and base regions are determined by the thickness of the solid phase growth layers, respectively.
    Type: Grant
    Filed: January 24, 1989
    Date of Patent: August 1, 1989
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shin-ichi Taka, Jiro Ohshima
  • Patent number: 4853760
    Abstract: A semiconductor device has a passivation layer including a polyimide film. Argon ions are implanted in the polyimide film to convert it into an electrically stable insulating film.
    Type: Grant
    Filed: August 25, 1987
    Date of Patent: August 1, 1989
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventors: Masahiro Abe, Masaharu Aoyama, Jiro Ohshima, Takashi Ajima
  • Patent number: 4780426
    Abstract: A first silicon oxide film is formed on the major surface of an n-type silicon substrate. A silicon nitride film is formed on the first silicon oxide film. The first silicon oxide film and the silicon nitride film are selectively etched to form an opening. Boron ions are implanted into the silicon substrate using the first silicon oxide film and the silicon nitride film as a mask. A second silicon oxide film is formed on the silicon substrate exposed by the opening. Gallium ions are implanted into the second silicon oxide film using the silicon nitride film as a mask. Boron and gallium ions are simultaneously diffused in the silicon substrate. In this case, a diffusion rate of gallium in the silicon substrate is higher than that of boron in the silicon substrate, and the diffusion rate of gallium in the silicon oxide film is higher than that in the silicon substrate. Therefore, a p-type second layer is formed in the substrate to surround a p.sup.+ -type first layer in a self-aligned manner.
    Type: Grant
    Filed: September 24, 1987
    Date of Patent: October 25, 1988
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yutaka Koshino, Yoshiro Baba, Jiro Ohshima
  • Patent number: 4766086
    Abstract: In a method of manufacturing a semiconductor device according to the present invention, a given position of a thermal oxide film formed on a monocrystalline silicon layer is opened to expose a surface of the monocrystalline silicon layer to serve as a getter site, a polycrystalline silicon layer is deposited on the thermal oxide film and the surface of the monocrystalline silicon layer, and the polycrystalline silicon layer is oxidized to convert the surface of the monocrystalline silicon layer directly contacting the polycrystalline silicon layer into an oxide film by thermal oxidation. That is, the position of interface between the oxide film and the monocrystalline silicon layer is shifted into the original monocrystalline silicon layer. During thermal oxidation of the polycrystalline silicon layer, a plurality of crystal defects to serve as getter sites are generated deeper than those generated by a conventional implagetter method in the monocrystalline silicon layer.
    Type: Grant
    Filed: March 2, 1987
    Date of Patent: August 23, 1988
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Jiro Ohshima, Shin-ichi Taka, Toshiyo Ito, Masaharu Aoyama
  • Patent number: 4717682
    Abstract: A method of manufacturing a semiconductor device, comprising the steps of sequentially forming a buried region and an epitaxial layer on a major surface of a semiconductor substrate, forming a conductive layer along an annular trench extending to the buried region, filling the annular trench with an insulating material and forming a functional element in said epitaxial layer surrounded by said buried region and said insulating material within said annular trench. In this method, the step of forming the conductive layer along the annular trench is carried out by the steps of forming an annular trench extending through said buried region, and depositing a conductive layer on only a side wall surface of said annular trench.
    Type: Grant
    Filed: February 19, 1986
    Date of Patent: January 5, 1988
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shin-ichi Taka, Jiro Ohshima, Masahiro Abe, Masaharu Aoyama
  • Patent number: 4543707
    Abstract: A process of manufacturing a semiconductor device by which a through hole such as contact hole with an obtuse opening edge can be formed in an insulation or passivation layer. At least two silicon oxynitride layers in which the nitrogen to oxygen ratio differs from each other are formed on a semiconductor substrate. The etching rate of the top layer is greater than that of the second layer from the top. The stacked silicon oxynitride layers are then selectively etched to form a through hole with an obtuse opening edge.
    Type: Grant
    Filed: June 29, 1984
    Date of Patent: October 1, 1985
    Assignee: Kabushiki Kaisha
    Inventors: Toshiyo Ito, Jiro Ohshima
  • Patent number: 4515642
    Abstract: In a method of producing a semiconductor device, an alumina layer is formed directly on a principal surface of a silicon substrate; aluminum and silicon are ion-implanted through the alumina layer into said substrate; and the substrate is thereafter annealed. The ion-implanted silicon yields better crystalline structure and increases the solid solubility limit of aluminum.
    Type: Grant
    Filed: August 22, 1983
    Date of Patent: May 7, 1985
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventors: Takashi Ajima, Jiro Ohshima, Yutaka Koshino
  • Patent number: 4502207
    Abstract: A wiring material of a semiconductor device, which comprises aluminum as a major component and at least a surface layer of the wiring layer is alloyed with boron and silicon. A method for forming a wiring material of a semiconductor device, which comprises the steps of: forming a wiring pattern comprising aluminum as a major component on a semiconductor element; and ion-implanting one of boron and a mixture of boron and silicon in the wiring pattern and alloying at least a surface layer of the wiring pattern to form an alloy layer containing aluminum, boron and silicon.
    Type: Grant
    Filed: December 16, 1983
    Date of Patent: March 5, 1985
    Assignee: Toshiba Shibaura Denki Kabushiki Kaisha
    Inventors: Jiro Ohshima, Masahiro Abe, Yutaka Koshino
  • Patent number: 4479830
    Abstract: A method for manufacturing a semiconductor device is shown which includes a step of ion implanting an impurity into an impurity-region formation region of a semiconductor substrate. Before or after the ion implantation step, silicon ions are implanted in a dose of 1.times.10.sup.13 to 1.times.10.sup.15 /cm.sup.2 into the impurity-region formation region and then the silicon ions so implanted are subjected to an activation treatment to form an epitaxial grown protrusion on the surface of the substrate. The protrusion is used as an alignment mark in the subsequent mask alignment step for photolithography.
    Type: Grant
    Filed: January 31, 1983
    Date of Patent: October 30, 1984
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventors: Yutaka Koshino, Jiro Ohshima, Takashi Ajima, Toshio Yonezawa
  • Patent number: 4426234
    Abstract: The invention discloses a method for fabricating a semiconductor device comprising the steps of: forming, on an entire surface of a semiconductor substrate of one conductivity type, a first thin film of a diffusion coefficient greater than a diffusion coefficient of the substrate; forming, on an entire surface of the first thin film, a second thin film having a diffusion coefficient smaller than the diffusion coefficient of the first thin film; ion-implanting an impurity through the second thin film into the first thin film to form an impurity region, said impurity having a conductivity type opposite to the conductivity type of the substrate; and effecting annealing to set a junction depth of the impurity region to a predetermined value. According to the method of the invention, an impurity region having a desired sheet resistivity and a desired diffusion depth can be formed in the semiconductor substrate with excellent reproducibility and control.
    Type: Grant
    Filed: December 3, 1981
    Date of Patent: January 17, 1984
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventors: Jiro Ohshima, Yutaka Koshino, Takashi Ajima, Toshio Yonezawa
  • Patent number: 4415372
    Abstract: The invention provides a method for fabricating a semiconductor device which comprises the steps of ion-implanting an impurity into a monocrystalline semiconductor substrate; irradiating the region into which the impurity ions have been implanted with an accelerated electron beam under the conditions that the acceleration voltage is 20 to 200 KeV, and the current is 0.01 to 1 mA and the exposure dose is 10.sup.20 to 10.sup.15 /cm.sup.2 ; and carrying out annealing to form a semiconductor region of one conductivity type. According to the present invention, a semiconductor device can be fabricated which has fewer lattice defects and in which the lifetime of the carriers is long.
    Type: Grant
    Filed: October 20, 1981
    Date of Patent: November 15, 1983
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventors: Yutaka Koshino, Toshio Yonezawa, Takashi Ajima, Jiro Ohshima
  • Patent number: 4404736
    Abstract: A method for manufacturing a semiconductor device of mesa type comprises forming mesa recesses of predetermined depth around an element in the surface of a semiconductor body, forming on the back of semiconductor body a film for lessening the concentration of stress, filling glass powder into mesa recesses, and sintering glass powder to form glass insulators. According to the method of the present invention, cracks can be prevented from being caused in the semiconductor body and glass insulators formed in mesa recesses.
    Type: Grant
    Filed: November 9, 1981
    Date of Patent: September 20, 1983
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventors: Yutaka Koshino, Takashi Ajima, Jiro Ohshima, Masahiro Abe
  • Patent number: 4334349
    Abstract: Disclosed is a method of producing a semiconductor device, comprising the steps of (a) forming a first insulating layer consisting of a lower silicon oxide film and an upper slicon nitride film on the surface of a semiconductor substrate, (b) forming a second insulating layer consisting of silicon oxide on the first insulating layer, (c) forming a third insulating layer consisting of silicon nitride on the second insulating layer, (d) selectively removing the third insulating layer so as to form a mask used for forming a hole for an interconnection electrode, (e) etching away the exposed portion of the second insulating layer by using the mask so as to form the hole for the interconnection electrode, (f) forming a conductive material layer on the entire surface of the structure obtained by step (e), a contact hole formed in the first insulating layer after step (a) or (e) being filled with the conductive material so as to allow the conductive material layer disposed on the first insulating layer to be connect
    Type: Grant
    Filed: June 3, 1980
    Date of Patent: June 15, 1982
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventors: Masaharu Aoyama, Jiro Ohshima, Toshio Yonezawa