Patents by Inventor Ji-yeon Shin
Ji-yeon Shin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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ADHESIVE FILM, OPTICAL MEMBER COMPRISING THE SAME, AND OPTICAL DISPLAY APPARATUS COMPRISING THE SAME
Publication number: 20240076530Abstract: An adhesive film, an optical member including the same, and an optical display apparatus including the same are provided. An adhesive film includes a (meth)acrylic based copolymer, a (meth)acrylic based oligomer, and a curing agent and has a maximum shear strain of 50% or less at 60° C. and a peel strength of 600 gf/25 mm or more with respect to a polyimide based film at 25° C.Type: ApplicationFiled: August 23, 2023Publication date: March 7, 2024Inventors: Ji Yeon Kim, Do Young Kim, Dong Myeong Shin, Ji Young Han, Kyoung Gon Park, Il Jin Kim -
Patent number: 11924988Abstract: A display apparatus including a display and a supporter. The supporter being mounted on the display and configured to support the display and rotate the display module between a first position and a second position. The supporter including a drive motor, a first gear, and a detection sensor. The drive motor configured to supply a driving force to rotate the display. The first gear configured to rotate together with the display by receiving the driving force from the drive motor. The detection sensor configured to detect a rotation amount of a second gear configured to rotate in with the first gear.Type: GrantFiled: December 23, 2022Date of Patent: March 5, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyun Yong Choi, Young Chul Kim, Ji Su Kim, Hun Sung Kim, Sung Yong Park, Jin Soo Shin, Dae Sik Yoon, Yong Yeon Hwang
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Publication number: 20240067808Abstract: An aqueous dispersion composition according embodiments of the present invention includes an ethylene-carboxylic acid copolymer, an anti-blocking agent including a polymer wax included in a content of 5 wt % or more based on a weight of the ethylene-carboxylic acid copolymer, and an aqueous dispersion medium. A peak area corresponding to a melting point of 80° C. or less in a differential scanning calorimetry (DSC) graph is 50% or more. Blocking phenomenon is suppressed using the anti-blocking agent while achieving desired heat seal properties.Type: ApplicationFiled: September 29, 2020Publication date: February 29, 2024Inventors: Jae Eun Lee, Ji Sun Choi, Doh Yeon Park, Hai Jin Shin
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Publication number: 20240009421Abstract: An emotional care apparatus based on a sound and a method thereof are provided. The emotional care apparatus includes a sound output device that outputs a sound to speakers and a processor electrically connected with the sound output device. The processor selects an emotional care mode, separates a sound source for each instrument from music content based on the emotional care mode, distributes the sound source for each instrument to the speakers, and controls the sound output device to play and output the sound source for each instrument to the distributed speakers.Type: ApplicationFiled: November 5, 2022Publication date: January 11, 2024Inventors: Ki Chang Kim, Tae kun Yun, Eun Soo Jo, Dong Chul Park, Eun Ju Jeong, Ji Yeon Shin
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Publication number: 20240008786Abstract: A multisensory index system and an operation method thereof are provided. The multisensory index system is configured to derive quantitative parameters and qualitative parameters associated with an auditory sense and a tactile sense, and generate a multisensory index by analyzing a correlation between the quantitative parameters and the qualitative parameters associated with the auditory sense and the tactile sense.Type: ApplicationFiled: November 5, 2022Publication date: January 11, 2024Inventors: Ki Chang Kim, Dong Chul Park, Eun Ju Jeong, Ji Yeon Shin
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Patent number: 11804270Abstract: A non-volatile memory device includes a memory cell region including a first metal pad and a memory cell array including a plurality of memory cells, and a peripheral circuit region including a second metal pad and an output driver to output a data signal, and vertically connected to the memory cell region by the first metal pad and the second metal pad. The output driver includes a pull-up driver and a pull-down driver. The pull-up driver includes a first pull-up driver having a plurality of P-type transistors and a second pull-up driver having a plurality of N-type transistors. The pull-down driver includes a plurality of N-type transistors. One or more power supply voltages having different voltage levels are selectively applied to the pull-up driver. A first power supply voltage is applied to the first pull-up driver, and a second power supply voltage is applied to the second pull-up driver.Type: GrantFiled: August 30, 2021Date of Patent: October 31, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Ji-Yeon Shin, Jeong-Don Ihm, Byung-Hoon Jeong, Jung-June Park
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Patent number: 11651805Abstract: A memory package includes; a first memory chip including first memory pads, and a buffer chip including first buffer pads respectively connected with the first memory pads and second buffer pads connected with an external device. The buffer chip respectively communicates signals received via the second buffer pads to the first buffer pads in response to a swap enable signal having a disabled state, and the buffer chip swaps signals received via the second buffer pads to generate first swapped signals, and respectively communicates the first swapped signals to the first buffer pads in response to the swap enable signal having an enabled state.Type: GrantFiled: April 29, 2021Date of Patent: May 16, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Ji-Yeon Shin, Daehoon Na, Jonghwa Kim
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Publication number: 20220139432Abstract: A memory package includes; a first memory chip including first memory pads, and a buffer chip including first buffer pads respectively connected with the first memory pads and second buffer pads connected with an external device. The buffer chip respectively communicates signals received via the second buffer pads to the first buffer pads in response to a swap enable signal having a disabled state, and the buffer chip swaps signals received via the second buffer pads to generate first swapped signals, and respectively communicates the first swapped signals to the first buffer pads in response to the swap enable signal having an enabled state.Type: ApplicationFiled: April 29, 2021Publication date: May 5, 2022Inventors: JI-YEON SHIN, DAEHOON NA, JONGHWA KIM
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Patent number: 11322205Abstract: A method for programming a non-volatile memory device is provided. The method comprises applying a program word line voltage with a voltage level changed stepwise to a selected word line connected to a plurality of memory cells, and applying a program bit line voltage to a first bit line of a plurality of bit lines connected to a plurality of first memory cells, while the program word line voltage is applied to the selected word line. The program bit line voltage transitions from a first voltage level to one of a program inhibit voltage level, a program voltage level, and a second voltage level. The first and second voltage levels are between the program inhibit voltage level and program voltage level.Type: GrantFiled: March 18, 2020Date of Patent: May 3, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sang-Won Park, Sang-Wan Nam, Ji Yeon Shin, Won Bo Shim, Jung-Yun Yun, Ji Ho Cho, Sang Gi Hong
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Patent number: 11257531Abstract: Provided is a nonvolatile memory including a clock pin configured to receive an external clock signal during a duty correction circuit training period; a plurality of memory chips configured to perform a duty correction operation on an internal clock signal based on the external clock signal, the plurality of memory chips configured to perform the duty correction operation in parallel during the training period; and an input/output pin commonly connected to the plurality of memory chips, wherein each of the plurality of memory chips includes: a duty correction circuit (DCC) configured to perform the duty correction operation on the internal clock signal; and an output buffer connected between an output terminal of the DCC and the input/output pin.Type: GrantFiled: January 27, 2021Date of Patent: February 22, 2022Assignee: Samsung Electronics Co., Ltd.Inventors: Jung-june Park, Jeong-don Ihm, Byung-hoon Jeong, Eun-ji Kim, Ji-yeon Shin, Young-don Choi
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Apparatus and method for providing cooperative shopping service in association with chat application
Patent number: 11232499Abstract: An apparatus that provides a cooperative shopping service in association with a chat application includes a friend information receiving unit configured to receive, from a host device, information about at least one friend or chat room selected from a list of multiple friends or multiple chat rooms managed by the chat application; an invitation unit configured to transmit an invitation message to a guest device corresponding to the friend or a member of the chat room through the chat application; and a cooperative shopping service providing unit configured to provide, both to the host device and the guest device, a list of products that are capable of being put into a shopping cart of the host device and receive order information about product selected from the list of products by at least one of the host device and the guest device, wherein the list of products provided to the host device and the guest device is generated based on a location of a delivery destination determined by the host device.Type: GrantFiled: April 16, 2018Date of Patent: January 25, 2022Assignee: KAKAO CORP.Inventors: Do Yon Hwang, Kyoung Jin Han, Jun Hwan Lee, Dong Wha Yuk, Woo Yeol Baek, Ji Yoong Choi, Ji Yeon Shin, Yeon Hee Shin, Mi Ran Kang, Sheung Min Shin, Yun Ji Koh, Du Hyeong Kim, Chang Sung Ban, Hyun Hee Park, Ji Eun Kim, Jin Young Choi -
Publication number: 20210391023Abstract: A non-volatile memory device includes a memory cell region including a first metal pad and a memory cell array including a plurality of memory cells, and a peripheral circuit region including a second metal pad and an output driver to output a data signal, and vertically connected to the memory cell region by the first metal pad and the second metal pad. The output driver includes a pull-up driver and a pull-down driver. The pull-up driver includes a first pull-up driver having a plurality of P-type transistors and a second pull-up driver having a plurality of N-type transistors. The pull-down driver includes a plurality of N-type transistors. One or more power supply voltages having different voltage levels are selectively applied to the pull-up driver. A first power supply voltage is applied to the first pull-up driver, and a second power supply voltage is applied to the second pull-up driver.Type: ApplicationFiled: August 30, 2021Publication date: December 16, 2021Inventors: Ji-yeon SHIN, Jeong-don IHM, Byung-hoon JEONG, Jung-june PARK
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Patent number: 11200952Abstract: A non-volatile memory device comprises a memory cell region including a first metal pad, a peripheral circuit region including a second metal pad and vertically connected to the memory cell region by the first metal pad and the second metal pad, a memory cell array in the memory cell region including a plurality of memory cells, each of the memory cells being connected to a plurality of word lines in the memory cell region and a plurality of bit lines in the memory cell region, and a control logic circuit in the peripheral circuit region configured to control voltages to be applied to the plurality of word lines and the plurality of bit lines.Type: GrantFiled: August 12, 2020Date of Patent: December 14, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sang-Won Park, Sang-Wan Nam, Ji Yeon Shin, Won Bo Shim, Jung-Yun Yun, Ji Ho Cho, Sang Gi Hong
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Patent number: 11114171Abstract: A non-volatile memory device includes a memory cell region including a first metal pad and a memory cell array including a plurality of memory cells, and a peripheral circuit region including a second metal pad and an output driver to output a data signal, and vertically connected to the memory cell region by the first metal pad and the second metal pad. The output driver includes a pull-up driver and a pull-down driver. The pull-up driver includes a first pull-up driver having a plurality of P-type transistors and a second pull-up driver having a plurality of N-type transistors. The pull-down driver includes a plurality of N-type transistors. One or more power supply voltages having different voltage levels are selectively applied to the pull-up driver. A first power supply voltage is applied to the first pull-up driver, and a second power supply voltage is applied to the second pull-up driver.Type: GrantFiled: September 2, 2020Date of Patent: September 7, 2021Assignee: Samsung Electronics Co., Ltd.Inventors: Ji-yeon Shin, Jeong-don Ihm, Byung-hoon Jeong, Jung-june Park
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Publication number: 20210151089Abstract: Provided is a nonvolatile memory including a clock pin configured to receive an external clock signal during a duty correction circuit training period; a plurality of memory chips configured to perform a duty correction operation on an internal clock signal based on the external clock signal, the plurality of memory chips configured to perform the duty correction operation in parallel during the training period; and an input/output pin commonly connected to the plurality of memory chips, wherein each of the plurality of memory chips includes: a duty correction circuit (DCC) configured to perform the duty correction operation on the internal clock signal; and an output buffer connected between an output terminal of the DCC and the input/output pin.Type: ApplicationFiled: January 27, 2021Publication date: May 20, 2021Applicant: Samsung Electronics Co., Ltd.Inventors: Jung-june Park, Jeong-don Ihm, Byung-hoon Jeong, Eun-ji Kim, Ji-yeon Shin, Young-don Choi
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Patent number: 10937474Abstract: Provided is a nonvolatile memory including a clock pin configured to receive an external clock signal during a duty correction circuit training period; a plurality of memory chips configured to perform a duty correction operation on an internal clock signal based on the external clock signal, the plurality of memory chips configured to perform the duty correction operation in parallel during the training period; and an input/output pin commonly connected to the plurality of memory chips, wherein each of the plurality of memory chips includes: a duty correction circuit (DCC) configured to perform the duty correction operation on the internal clock signal; and an output buffer connected between an output terminal of the DCC and the input/output pin.Type: GrantFiled: October 30, 2019Date of Patent: March 2, 2021Assignee: Samsung Electronics Co., Ltd.Inventors: Jung-june Park, Jeong-don Ihm, Byung-hoon Jeong, Eun-ji Kim, Ji-yeon Shin, Young-don Choi
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Publication number: 20210027840Abstract: A method for programming a non-volatile memory device is provided. The method comprises applying a program word line voltage with a voltage level changed stepwise to a selected word line connected to a plurality of memory cells, and applying a program bit line voltage to a first bit line of a plurality of bit lines connected to a plurality of first memory cells, while the program word line voltage is applied to the selected word line. The program bit line voltage transitions from a first voltage level to one of a program inhibit voltage level, a program voltage level, and a second voltage level. The first and second voltage levels are between the program inhibit voltage level and program voltage level.Type: ApplicationFiled: March 18, 2020Publication date: January 28, 2021Inventors: Sang-Won PARK, Sang-Wan NAM, Ji Yeon SHIN, Won Bo SHIM, Jung-Yun YUN, Ji Ho CHO, Sang Gi HONG
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Publication number: 20210027841Abstract: A non-volatile memory device comprises a memory cell region including a first metal pad, a peripheral circuit region including a second metal pad and vertically connected to the memory cell region by the first metal pad and the second metal pad, a memory cell array in the memory cell region including a plurality of memory cells, each of the memory cells being connected to a plurality of word lines in the memory cell region and a plurality of bit lines in the memory cell region, and a control logic circuit in the peripheral circuit region configured to control voltages to be applied to the plurality of word lines and the plurality of bit lines.Type: ApplicationFiled: August 12, 2020Publication date: January 28, 2021Inventors: Sang-Won PARK, Sang-Wan NAM, Ji Yeon SHIN, Won Bo SHIM, Jung-Yun YUN, Ji Ho CHO, Sang Gi HONG
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Publication number: 20200402592Abstract: A non-volatile memory device includes a memory cell region including a first metal pad and a memory cell array including a plurality of memory cells, and a peripheral circuit region including a second metal pad and an output driver to output a data signal, and vertically connected to the memory cell region by the first metal pad and the second metal pad. The output driver includes a pull-up driver and a pull-down driver. The pull-up driver includes a first pull-up driver having a plurality of P-type transistors and a second pull-up driver having a plurality of N-type transistors. The pull-down driver includes a plurality of N-type transistors. One or more power supply voltages having different voltage levels are selectively applied to the pull-up driver. A first power supply voltage is applied to the first pull-up driver, and a second power supply voltage is applied to the second pull-up driver.Type: ApplicationFiled: September 2, 2020Publication date: December 24, 2020Inventors: Ji-yeon SHIN, Jeong-don IHM, Byung-hoon JEONG, Jung-june PARK
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Patent number: 10770149Abstract: A non-volatile memory device includes an output driver to output a data signal. The output driver includes a pull-up driver and a pull-down driver. The pull-up driver includes a first pull-up driver having a plurality of P-type transistors and a second pull-up driver having a plurality of N-type transistors. The pull-down driver includes a plurality of N-type transistors. One or more power supply voltages having different voltage levels are selectively applied to the pull-up driver. A first power supply voltage is applied to the first pull-up driver, and a second power supply voltage is applied to the second pull-up driver.Type: GrantFiled: July 30, 2018Date of Patent: September 8, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Ji-yeon Shin, Jeong-don Ihm, Byung-hoon Jeong, Jung-june Park