Patents by Inventor Joachim Mahler

Joachim Mahler has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170338169
    Abstract: In various embodiments, a chip package is provided. The chip package may include a chip, a metal contact structure including a non-noble metal and electrically contacting the chip, a packaging material, and a protective layer including or essentially consisting of a portion formed at an interface between a portion of the metal contact structure and the packaging material, wherein the protective layer may include a noble metal, wherein the portion of the protective layer may include a plurality of regions free from the noble metal, and wherein the regions free from the noble metal may provide an interface between the packaging material and the non-noble metal of the metal contact structure.
    Type: Application
    Filed: May 22, 2017
    Publication date: November 23, 2017
    Inventors: Joachim Mahler, Michael Bauer, Jochen Dangelmaier, Reimund Engl, Johann Gatterbauer, Frank Hille, Michael Huettinger, Werner Kanert, Heinrich Koerner, Brigitte Ruehle, Francisco Javier Santos Rodriguez, Antonio Vellei
  • Patent number: 9825023
    Abstract: An embodiment of an IGBT comprises an emitter terminal at a first surface of a semiconductor body. The IGBT further comprises a collector terminal at a second surface of the semiconductor body. A first zone of a first conductivity type is in the semiconductor body between the first and second surfaces. A collector injection structure adjoins the second surface, the collector injection structure being of a second conductivity type and comprising a first part and a second part at a first lateral distance from each other. The IGBT further comprises a negative temperature coefficient thermistor adjoining the first zone in an area between the first and second parts.
    Type: Grant
    Filed: October 12, 2015
    Date of Patent: November 21, 2017
    Assignee: Infineon Technologies Austria AG
    Inventors: Thomas Basler, Erich Griebl, Joachim Mahler, Daniel Pedone, Wolfgang Scholz, Philipp Seng, Peter Tuerkes, Stephan Voss
  • Patent number: 9793255
    Abstract: A power semiconductor device includes a wiring structure adjoining at least one side of a semiconductor body and comprising at least one electrically conductive compound. The power semiconductor device further includes a cooling material in the wiring structure. The cooling material is characterized by a change in structure by means of absorption of energy at a temperature TC ranging between 150° C. and 400° C.
    Type: Grant
    Filed: January 13, 2015
    Date of Patent: October 17, 2017
    Assignee: Infineon Technologies AG
    Inventors: Joachim Mahler, Ralf Otremba, Hans-Joachim Schulze, Guenther Ruhl, Hans-Joerg Timme
  • Patent number: 9790086
    Abstract: A micromechanical semiconductor sensing device is disclosed. In an embodiment the sensing device includes a micromechanical sensing structure being configured to yield an electrical sensing signal, and a piezoresistive sensing device provided in the micromechanical sensing structure, the piezoresistive sensing device being arranged to sense a mechanical stress disturbing the electrical sensing signal and being configured to yield an electrical disturbance signal based on the sensed mechanical stress disturbing the electrical sensing signal.
    Type: Grant
    Filed: September 16, 2016
    Date of Patent: October 17, 2017
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Franz-Peter Kalz, Horst Theuss, Bernhard Winkler, Khalil Hosseini, Joachim Mahler, Manfred Mengel
  • Publication number: 20170256472
    Abstract: A package which comprises a first encapsulant configured so that electrically conductive material is plateable thereon, and a second encapsulant configured so that electrically conductive material is not plateable thereon.
    Type: Application
    Filed: March 2, 2017
    Publication date: September 7, 2017
    Inventors: Sook Woon CHAN, Chau Fatt CHIANG, Kok Yau CHUA, Soon Lock GOH, Swee Kah LEE, Joachim MAHLER, Mei Chin NG, Beng Keh SEE, Guan Choon Matthew Nelson TEE
  • Publication number: 20170221857
    Abstract: A method of manufacturing a package which comprises encapsulating at least part of an electronic chip by an encapsulant, subsequently covering a part of the electronic chip with a chip attach medium, and attaching the encapsulated electronic chip on a chip carrier via the chip attach medium.
    Type: Application
    Filed: February 2, 2017
    Publication date: August 3, 2017
    Inventors: Joachim MAHLER, Edward FUERGUT, Georg MEYER-BERG
  • Publication number: 20170208684
    Abstract: A printed circuit board includes an electrically conductive layer and a dielectric layer including a polymer. The polymer includes at least one of a carbon layer structure and a carbon-like layer structure.
    Type: Application
    Filed: March 31, 2017
    Publication date: July 20, 2017
    Inventors: Joachim Mahler, Ralf Otremba
  • Publication number: 20170186663
    Abstract: A semiconductor device includes a drift structure formed in a semiconductor body. The drift structure forms a first pn junction with a body zone of a transistor cell. A gate structure extends from a first surface of the semiconductor body into the drift structure. A heat sink structure extends from the first surface into the drift structure. A thermal conductivity of the heat sink structure is greater than a thermal conductivity of the gate structure and/or a thermal capacity of the heat sink structure is greater than a thermal capacity of the gate structure.
    Type: Application
    Filed: December 16, 2016
    Publication date: June 29, 2017
    Inventors: Johannes Georg Laven, Peter Irsigler, Joachim Mahler, Guenther Ruhl, Hans-Joachim Schulze, Markus Zundel
  • Patent number: 9673170
    Abstract: Methods for connecting chips to a chip carrier are disclosed. In some embodiments the method for connecting a plurality of chips to a chip carrier includes placing first chips on a transfer carrier, placing second chips on the transfer carrier, placing the transfer carrier with the first and second chips on the chip carrier and forming connections between the first chips and the chip carrier and the second chips and the chip carrier.
    Type: Grant
    Filed: August 5, 2014
    Date of Patent: June 6, 2017
    Assignee: Infineon Technologies AG
    Inventors: Rupert Fischer, Peter Strobel, Joachim Mahler, Konrad Roesl, Alexander Heinrich
  • Patent number: 9666499
    Abstract: Described are techniques related to semiconductor devices that make use of encapsulant. In one implementation, a semiconductor device may be manufactured to include at least an encapsulant that includes at least glass particles.
    Type: Grant
    Filed: October 31, 2012
    Date of Patent: May 30, 2017
    Assignee: Infineon Technologies AG
    Inventors: Joachim Mahler, Edward Fuergut, Khalil Hosseini, Georg Meyer-Berg
  • Patent number: 9666452
    Abstract: A method for manufacturing a chip package is provided. The method including: holding a carrier including a plurality of dies; forming a separation between the plurality of dies by removing from the carrier one or more portions of the carrier between the plurality of dies; forming an encapsulation material in the removed one or more portions between the plurality of dies; separating the dies through the encapsulation material.
    Type: Grant
    Filed: May 25, 2012
    Date of Patent: May 30, 2017
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Karl Adolf Dieter Mayer, Guenter Tutsch, Horst Theuss, Manfred Engelhardt, Joachim Mahler
  • Patent number: 9660029
    Abstract: A semiconductor device includes a first load terminal at a first surface of a semiconductor body and a second load terminal at the opposing surface. An active device area is surrounded by an edge termination area. Load terminal contacts are absent in the edge termination area and are electrically connected to the semiconductor body in the active device area at the first surface. A positive temperature coefficient structure is between at least one of the first and second load terminals and a corresponding one of the first and second surfaces. Above a maximum operation temperature specified for the semiconductor device, a specific resistance of the positive temperature coefficient structure increases by at least two orders of magnitude within a temperature range of at most 50 K. A degree of area coverage of the positive temperature coefficient structure is greater in the edge termination area than in the active device area.
    Type: Grant
    Filed: November 16, 2015
    Date of Patent: May 23, 2017
    Assignee: Infineon Technologies Austria AG
    Inventors: Thomas Basler, Hans-Joachim Schulze, Johannes Georg Laven, Joachim Mahler
  • Patent number: 9648735
    Abstract: A printed circuit board includes an electrically conductive layer and a dielectric layer including a polymer, wherein the polymer includes metallic particles.
    Type: Grant
    Filed: June 3, 2015
    Date of Patent: May 9, 2017
    Assignee: Infineon Technologies AG
    Inventors: Joachim Mahler, Ralf Otremba
  • Patent number: 9633927
    Abstract: A chip arrangement includes semiconductor chips coupled to opposing sides of an insulating layer. The arrangement includes a first semiconductor chip having a first chip surface presenting a first chip conductive region. An electrically insulating layer includes a first layer surface presenting a first layer conductive region, and a second, opposing surface presenting a second layer conductive region. The electrically insulating layer is coupled to the first semiconductor chip by applying the first layer conductive region to the first chip conductive region. The electrically insulating layer is then coupled to the second chip conductive region by applying the second layer conductive region to the second chip conductive region.
    Type: Grant
    Filed: August 14, 2013
    Date of Patent: April 25, 2017
    Assignee: Infineon Technologies AG
    Inventors: Joachim Mahler, Alfred Haimerl, Angela Kessler, Michael Bauer
  • Publication number: 20170082502
    Abstract: Temperature sensor devices and corresponding methods are provided. A temperature sensor may include a first layer being essentially non-conductive in a temperature range and a second layer having a varying resistance in the temperature range.
    Type: Application
    Filed: December 5, 2016
    Publication date: March 23, 2017
    Inventors: Christian Kegler, Johannes Georg Laven, Hans-Joachim Schulze, Guenther Ruhl, Joachim Mahler
  • Patent number: 9583413
    Abstract: A semiconductor device includes a first chip coupled to an electrical insulator, and a sintered heat conducting layer disposed between the electrical insulator and the first chip.
    Type: Grant
    Filed: February 13, 2009
    Date of Patent: February 28, 2017
    Assignee: Infineon Technologies AG
    Inventors: Ivan Nikitin, Joachim Mahler, Thomas Behrens
  • Patent number: 9576944
    Abstract: A semiconductor device includes a first load terminal electrically coupled to a source zone of a transistor cell. A gate terminal is electrically coupled to a gate electrode which is capacitively coupled to a body zone of the transistor cell. The source and body zones are formed in a semiconductor portion. A thermoresistive element is thermally connected to the semiconductor portion and is electrically coupled between the gate terminal and the first load terminal. Above a maximum operation temperature specified for the semiconductor device, an electric resistance of the thermoresistive element decreases by at least two orders of magnitude within a critical temperature span of at most 50 Kelvin.
    Type: Grant
    Filed: December 4, 2015
    Date of Patent: February 21, 2017
    Assignee: Infineon Technologies AG
    Inventors: Johannes Georg Laven, Christian Jaeger, Joachim Mahler, Daniel Pedone, Anton Prueckl, Hans-Joachim Schulze, Andre Schwagmann, Patrick Schwarz
  • Patent number: 9567211
    Abstract: Micromechanical semiconductor sensing device comprises a micromechanical sensing structure being configured to yield an electrical sensing signal, and a piezoresistive sensing device provided in the micromechanical sensing structure, said piezoresistive sensing device being arranged to sense a mechanical stress disturbing the electrical sensing signal and being configured to yield an electrical disturbance signal based on the sensed mechanical stress disturbing the electrical sensing signal.
    Type: Grant
    Filed: April 15, 2015
    Date of Patent: February 14, 2017
    Assignee: Infineon Technologies AG
    Inventors: Franz-Peter Kalz, Horst Theuss, Bernhard Winkler, Khalil Hosseini, Joachim Mahler, Manfred Mengel
  • Publication number: 20170040431
    Abstract: A semiconductor device includes at least one highly doped region of an electrical device arrangement formed in a semiconductor substrate and a contact structure including an NTC (negative temperature coefficient of resistance) portion arranged adjacent to the at least one highly doped region at a front side surface of the semiconductor substrate. The NTC portion includes a negative temperature coefficient of resistance material.
    Type: Application
    Filed: August 5, 2016
    Publication date: February 9, 2017
    Inventors: Thomas Basler, Joachim Mahler, Hans-Joachim Schulze
  • Patent number: 9559078
    Abstract: An electronic component includes an electrically conductive carrier. The electrically conductive carrier includes a carrier surface and a semiconductor chip includes a chip surface. One or both of the carrier surface and the chip surface include a non-planar structure. The chip is attached to the carrier with the chip surface facing towards the carrier surface so that a gap is provided between the chip surface and the carrier surface due to the non-planar structure of one or both of the carrier surface and the first chip surface. The electronic component further includes a first galvanically deposited metallic layer situated in the gap.
    Type: Grant
    Filed: December 23, 2014
    Date of Patent: January 31, 2017
    Assignee: Infineon Technologies AG
    Inventors: Joachim Mahler, Manfred Mengel, Khalil Hosseini, Klaus Schmidt, Franz-Peter Kalz