Patents by Inventor Joaquim J. Machado

Joaquim J. Machado has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • High speed PLL clock multiplier
    Patent number: 7940128
    Abstract: The present invention relates to a mixed mode electronic circuit that implements a PLL cell that employs an auto-range algorithm to lock to a wide range of input reference signals.
    Type: Grant
    Filed: September 16, 2008
    Date of Patent: May 10, 2011
    Assignee: Synopsys, Inc.
    Inventor: Joaquim J. Machado
  • HIGH SPEED PLL CLOCK MULTIPLIER
    Publication number: 20090284318
    Abstract: The present invention relates to a mixed mode electronic circuit that implements a PLL cell that employs an auto-range algorithm to lock to a wide range of input reference signals.
    Type: Application
    Filed: September 16, 2008
    Publication date: November 19, 2009
    Applicant: MIPSABG Chipidea, Lda.
    Inventor: Joaquim J. Machado