Patents by Inventor Jochen Beintner

Jochen Beintner has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080111184
    Abstract: A method of fabricating a plurality of FinFETs on a semiconductor substrate in which the gate width of each individual FinFET is defined utilizing only a single etching process, instead of two or more, is provided. The inventive method results in improved gate width control and less variation of the gate width of each individual gate across the entire surface of the substrate. The inventive method achieves the above by utilizing a modified sidewall image transfer (SIT) process in which an insulating spacer that is later replaced by a gate conductor is employed and a high-density bottom up oxide fill is used to isolate the gate from the substrate.
    Type: Application
    Filed: November 14, 2006
    Publication date: May 15, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jochen Beintner, Gary B. Bronner, Ramachandra Divakaruni, Yujun Li
  • Patent number: 7348641
    Abstract: A gated semiconductor device is provided, in which the body has a first dimension extending in a lateral direction parallel to a major surface of a substrate, and second dimension extending in a direction at least substantially vertical and at least substantially perpendicular to the major surface, the body having a first side and a second side opposite the first side. The gated semiconductor device includes a first gate overlying the first side, and having a first gate length in the lateral direction. The gated semiconductor device further includes a second gate overlying the second side, the second gate having a second gate length in the lateral direction which is different from, and preferably shorter than the first gate length. In one embodiment, the first gate and the second gate being electrically isolated from each other. In another embodiment the first gate consists essentially of polycrystalline silicon germanium and the second gate consists essentially of polysilicon.
    Type: Grant
    Filed: August 31, 2004
    Date of Patent: March 25, 2008
    Assignee: International Business Machines Corporation
    Inventors: Huilong Zhu, Bruce B. Doris, Xinlin Wang, Jochen Beintner, Ying Zhang, Philip J. Oldiges
  • Patent number: 7346887
    Abstract: The present invention is directed to a method for conversion of an integrated circuit design into a set of masks for fabrication of an integrated circuit that optimizes use of an edge based image transfer mask process.
    Type: Grant
    Filed: November 9, 2005
    Date of Patent: March 18, 2008
    Assignee: International Business Machines Corporation
    Inventors: Lars W. Liebmann, Jochen Beintner
  • Patent number: 7323374
    Abstract: A method, structure and alignment procedure, for forming a finFET. The method including, defining a first fin of the finFET with a first mask and defining a second fin of the finFET with a second mask. The structure including integral first and second fins of single-crystal semiconductor material and longitudinal axes of the first and second fins aligned in the same crystal direction but offset from each other. The alignment procedure including simultaneously aligning alignment marks on a gate mask to alignment targets formed separately by a first masked used to define the first fin and a second mask used to define the second fin.
    Type: Grant
    Filed: September 19, 2005
    Date of Patent: January 29, 2008
    Assignee: International Business Machines Corporation
    Inventors: Jochen Beintner, Thomas Ludwig, Edward Joseph Nowak
  • Publication number: 20080006852
    Abstract: A method, structure and alignment procedure, for forming a finFET. The method including, defining a first fin of the finFET with a first mask and defining a second fin of the finFET with a second mask. The structure including integral first and second fins of single-crystal semiconductor material and longitudinal axes of the first and second fins aligned in the same crystal direction but offset from each other. The alignment procedure including simultaneously aligning alignment marks on a gate mask to alignment targets formed separately by a first masked used to define the first fin and a second mask used to define the second fin.
    Type: Application
    Filed: September 19, 2007
    Publication date: January 10, 2008
    Inventors: Jochen Beintner, Thomas Ludwig, Edward Nowak
  • Publication number: 20070181930
    Abstract: A gated semiconductor device is provided, in which the body has a first dimension extending in a lateral direction parallel to a major surface of a substrate, and second dimension extending in a direction at least substantially vertical and at least substantially perpendicular to the major surface, the body having a first side and a second side opposite the first side. The gated semiconductor device includes a first gate overlying the first side, and having a first gate length in the lateral direction. The gated semiconductor device further includes a second gate overlying the second side, the second gate having a second gate length in the lateral direction which is different from, and preferably shorter than the first gate length. In one embodiment, the first gate and the second gate being electrically isolated from each other. In another embodiment the first gate consists essentially of polycrystalline silicon germanium and the second gate consists essentially of polysilicon.
    Type: Application
    Filed: August 31, 2004
    Publication date: August 9, 2007
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Huilong Zhu, Bruce Doris, Xinlin Wang, Jochen Beintner, Ying Zhang, Philip Oldiges
  • Publication number: 20070167024
    Abstract: A method is presented for fabricating a non-planar field effect device. The method includes the production of a Si based material Fin structure that has a top surface substantially in parallel with a {111} crystallographic plane of the Si Fin structure, and the etching of the Si Fin structure with a solution which contains ammonium hydroxide (NH4OH). In this manner, due to differing etch rates in ammonium hydroxide of various Si based material crystallographic planes, the corners on the Fin structure become clipped, and angles between the horizontal and vertical planes of the Fin structure increase. A FinFET device with clipped, or rounded, corners is then fabricated to completion. In a typical embodiment the FinFET device is selected to be a silicon-on-insulator (SOI) device.
    Type: Application
    Filed: January 17, 2006
    Publication date: July 19, 2007
    Applicant: International Business Machines Corporation
    Inventors: Yujun Li, Kenneth Settlemyer, Jochen Beintner
  • Publication number: 20070166900
    Abstract: A method of fabrication and a field effect device structure are presented that reduce source/drain capacitance and allow for device body contact. A Si based material pedestal is produced, the top surface and the sidewalls of which are oriented in a way to be substantially parallel with selected crystallographic planes of the pedestal and of a supporting member. The pedestal is wet etched with an anisotropic solution containing ammonium hydroxide. The sidewalls of the pedestal become faceted forming a segment in the pedestal with a reduced cross section. The dopant concentration in the reduced cross section segment is chosen to be sufficiently high for it to provide for electrical continuity through the pedestal.
    Type: Application
    Filed: January 17, 2006
    Publication date: July 19, 2007
    Applicant: International Business Machines Corporation
    Inventors: Yujun Li, Kenneth Settlemyer, Jochen Beintner
  • Publication number: 20070106972
    Abstract: The present invention is directed to a method for conversion of an integrated circuit design into a set of masks for fabrication of an integrated circuit that optimizes use of an edge based image transfer mask process.
    Type: Application
    Filed: November 9, 2005
    Publication date: May 10, 2007
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Lars Liebmann, Jochen Beintner
  • Publication number: 20070063276
    Abstract: A method, structure and alignment procedure, for forming a finFET. The method including, defining a first fin of the finFET with a first mask and defining a second fin of the finFET with a second mask. The structure including integral first and second fins of single-crystal semiconductor material and longitudinal axes of the first and second fins aligned in the same crystal direction but offset from each other. The alignment procedure including simultaneously aligning alignment marks on a gate mask to alignment targets formed separately by a first masked used to define the first fin and a second mask used to define the second fin.
    Type: Application
    Filed: September 19, 2005
    Publication date: March 22, 2007
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jochen Beintner, Thomas Ludwig, Edward Nowak
  • Patent number: 7157329
    Abstract: A trench capacitor with improved strap is disclosed. The strap is located above the top surface of the capacitor. The top surface of the trench capacitor, which is formed by the top surfaces of the collar and storage plate, is planar. By locating the strap on a planar surface, the divot present in conventional strap processes is avoided. This results in improved strap reliability and device performance.
    Type: Grant
    Filed: February 8, 2005
    Date of Patent: January 2, 2007
    Assignee: Infineon Technologies Aktiengesellschaft
    Inventors: Helmut Tews, Jochen Beintner, Stephan Kudelka
  • Patent number: 7129564
    Abstract: The structure and method of forming a notched gate MOSFET disclosed herein addresses such problems as device reliability. A gate dielectric (e.g. gate oxide) is formed on the surface of an active area on the semiconductor substrate, preferably defined by an isolation trench region. A layer of polysilicon is then deposited on the gate dielectric. This step is followed by depositing a layer of silicon germanium) (SiGe). The sidewalls of the polysilicon layer are then laterally etched, selective to the SiGe layer to create a notched gate conductor structure, with the SiGe layer being broader than the underlying polysilicon layer. Sidewall spacers are preferably formed on sidewalls of the SiGe layer and the polysilicon layer. A silicide layer is preferably formed as a self-aligned silicide from a polysilicon layer deposited over the SiGe layer, to reduce resistance of the gate conductor. One or more other processing steps (e.g.
    Type: Grant
    Filed: February 17, 2005
    Date of Patent: October 31, 2006
    Assignee: International Business Machines Corporation
    Inventors: Jochen Beintner, Yujun Li, Naim Moumen, Porshia Shane Wrschka
  • Patent number: 7101755
    Abstract: A method for processing a semiconductor device includes providing the semiconductor device including a deep trench transistor in an array area and a shallow trench isolation oxide in a support area, wherein a pad oxide and pad nitride are sequentially formed on a semiconductor substrate. The method includes stripping the pad nitride, depositing an array top oxide layer over the pad oxide formed on the semiconductor substrate in the array area and the support area, and planarizing the array top oxide to a top of the shallow trench isolation oxide in the support area and to a deep trench poly stud of the deep trench transistor in the array area. The method further includes forming a wordline stack comprising a nitride layer, a gate conductor and an insulator, and etching the array top oxide, forming a passing wordline bridge through the array area supported on the shallow trench isolation oxide.
    Type: Grant
    Filed: August 5, 2004
    Date of Patent: September 5, 2006
    Assignee: Infineon Technologies AG
    Inventor: Jochen Beintner
  • Patent number: 7091103
    Abstract: CMP of integrated circuits containing DRAM arrays with trench capacitors fill the trenches with oxide, resulting in a an array of oxide structures that is dense compared with the concentration in the surrounding support structures and therefore has a higher loading. A conformal layer is deposited over the wafer, increasing the loading in the array, but filling in spaces between active areas. A blanket etch removes material in both the array and the supports. A block etch balances the amount of material in the array and the supports. A supplementary oxide deposition in the array fills spaces between the structures to a nearly uniform density.
    Type: Grant
    Filed: December 9, 2002
    Date of Patent: August 15, 2006
    Assignees: International Business Machines Corporation, Infineon Technologies North America Corporation
    Inventors: Jochen Beintner, Laertis Economikos, Michael Wise, Andreas Knorr
  • Patent number: 7091566
    Abstract: A field effect transistor (FET), integrated circuit (IC) chip including the FETs and a method of forming the FETS. Each FET includes a device gate along one side of a semiconductor (e.g., silicon) fin and a back bias gate along an opposite of the fin. Back bias gate dielectric differs from the device gate dielectric either in its material and/or thickness. Device thresholds can be adjusted by adjusting back bias gate voltage.
    Type: Grant
    Filed: November 20, 2003
    Date of Patent: August 15, 2006
    Assignee: International Business Machines Corp.
    Inventors: Huilong Zhu, Jochen Beintner, Bruce B. Doris, Ying Zhang
  • Patent number: 7087952
    Abstract: A non-volatile storage cell in a Fin Field Effect Transistor (FinFET) and a method of forming an Integrated Circuit (IC) chip including the non-volatile storage cell. Each FET includes a control gate along one side of a semiconductor (e.g., silicon) fin, a floating gate along an opposite of the fin and a program gate alongside the floating gate. Control gate device thresholds are adjusted by adjusting charge on the floating gate.
    Type: Grant
    Filed: November 1, 2004
    Date of Patent: August 8, 2006
    Assignee: International Business Machines Corporation
    Inventors: Huilong Zhu, Bruce B. Doris, Jochen Beintner
  • Publication number: 20060157805
    Abstract: A structure and method of forming a notched gate MOSFET. A gate dielectric is formed on the surface of an active area on the semiconductor substrate. A layer of polysilicon is then deposited on the gate dielectric. This step is followed by depositing a layer of silicon germanium. The sidewalls of the polysilicon layer are then laterally etched, selective to the SiGe layer to create a notched gate conductor structure, with the SiGe layer being broader than the underlying polysilicon layer. Sidewall spacers are preferably formed on sidewalls of the SiGe layer and the polysilicon layer. A silicide layer is preferably formed as a self-aligned silicide from a polysilicon layer deposited over the SiGe layer. One or more other processing steps are preferably performed in completing the transistor.
    Type: Application
    Filed: November 4, 2005
    Publication date: July 20, 2006
    Applicants: INFINEON TECHNOLOGIES AG, International Business Machines Corporation
    Inventors: Jochen Beintner, Yujun Li, Naim Moumen, Porshia Wrschka
  • Publication number: 20060128111
    Abstract: The present invention provides a strained/SGOI structure that includes an active device region of a relaxed SiGe layer, a strained Si layer located atop the relaxed SiGe layer, a raised source/drain region located atop a portion of the strained Si layer, and a stack comprising at least a gate dielectric and a gate polySi located on another portion of the strained Si layer; and a raised trench oxide region surrounding the active device region. The present invention also provides a method of forming such a structure. In the inventive method, the gate dielectric is formed prior to trench isolation formation thereby avoiding many of the problems associated with prior art processes in which the trench oxide is formed prior to gate dielectric formation.
    Type: Application
    Filed: February 10, 2006
    Publication date: June 15, 2006
    Applicant: International Business Machines Corporation
    Inventors: Jochen Beintner, Gary Bronner, Ramachandra Divakaruni, Byeong Kim
  • Publication number: 20060091450
    Abstract: A non-volatile storage cell in a Fin Field Effect Transistor (FinFET) and a method of forming an Integrated Circuit (IC) chip including the non-volatile storage cell. Each FET includes a control gate along one side of a semiconductor (e.g., silicon) fin, a floating gate along an opposite of the fin and a program gate alongside the floating gate. Control gate device thresholds are adjusted by adjusting charge on the floating gate.
    Type: Application
    Filed: November 1, 2004
    Publication date: May 4, 2006
    Inventors: Huilong Zhu, Bruce Doris, Jochen Beintner
  • Patent number: 7037794
    Abstract: The present invention provides a strained/SGOI structure that includes an active device region of a relaxed SiGe layer, a strained Si layer located atop the relaxed SiGe layer, a raised source/drain region located atop a portion of the strained Si layer, and a stack comprising at least a gate dielectric and a gate polySi located on another portion of the strained Si layer; and a raised trench oxide region surrounding the active device region. The present invention also provides a method of forming such a structure. In the inventive method, the gate dielectric is formed prior to trench isolation formation thereby avoiding many of the problems associated with prior art processes in which the trench oxide is formed prior to gate dielectric formation.
    Type: Grant
    Filed: June 9, 2004
    Date of Patent: May 2, 2006
    Assignee: International Business Machines Corporation
    Inventors: Jochen Beintner, Gary B. Bronner, Ramachandra Divakaruni, Byeong Y. Kim