Patents by Inventor Joe Yamaguchi

Joe Yamaguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Material and method for planarization of substrate
    Patent number: 5976703
    Abstract: A material and a method for planarizing an uneven surface of a substrate, such as those used for making wiring boards and electronic devices and having broad patterns on their surfaces, are provided. The material is a polysilphenylenesiloxane or a copolymer of polysilphenylenesiloxane with an organosiloxane, and is applied to an uneven surface of a substrate, and then heated to be reflowed to thereby be formed into a planarized film or layer. The material allows a substrate containing wiring having a width of up to several hundred micrometers to be planarized.
    Type: Grant
    Filed: June 14, 1996
    Date of Patent: November 2, 1999
    Assignee: Fujitsu Limited
    Inventors: Yoshihiro Nakata, Shyun-ichi Fukuyama, Michiko Katayama, Joe Yamaguchi, Hideki Harada, Yoshiyuki Ohkura
  • Electrical connecting device and method for making same
    Patent number: 5746927
    Abstract: An electrical connecting device including a first circuit board providing thereon with input/output terminals, each of the terminals having a tip surface coated with gallium and a second circuit board providing thereon with contact terminals, each of the terminals having a tip surface coated with indium or tin. A low-melting point alloy layer is formed by a mutual action between gallium and indium or tin, when the input/output terminals of the first circuit board are in contact with the respective terminals of the second circuit board and the terminals are electrically connected to each other. The second metal layer includes a plurality of wire-like metal supports extending substantially perpendicular to the surface of the terminal and a low-melting point metal retained by the wire-like metal supports.
    Type: Grant
    Filed: December 12, 1996
    Date of Patent: May 5, 1998
    Assignee: Fujitsu Limited
    Inventors: Kaoru Hashimoto, Tatuo Chiyonobu, Kyoichiro Kawano, Koji Watanabe, Masato Wakamura, Joe Yamaguchi
  • Electrical connecting device and method for making same
    Patent number: 5610371
    Abstract: An electrical connecting device including a first circuit board providing thereon with input/output terminals, each of the terminals having a tip surface coated with gallium and a second circuit board providing thereon with contact terminals, each of the terminals having a tip surface coated with indium or tin. A low-melting point alloy layer is formed by a mutual action between gallium and indium or tin, when the input/output terminals of the first circuit board are in contact with the respective terminals of the second circuit board and the terminals are electrically connected to each other. The second metal layer includes a plurality of wire-like metal supports extending substantially perpendicular to the surface of the terminal and a low-melting point metal retained by the wire-like metal supports.
    Type: Grant
    Filed: March 14, 1995
    Date of Patent: March 11, 1997
    Assignee: Fujitsu Limited
    Inventors: Kaoru Hashimoto, Tatuo Chiyonobu, Kyoichiro Kawano, Koji Watanabe, Masato Wakamura, Joe Yamaguchi