Abstract: A method system, and computer program product for determining the source of a fault within a bus, such as, for example, an inter integrated circuit (I2C) bus is provided. In one embodiment, a bus driver monitors the bus for faults. If a fault occurs on the bus, the bus driver resets each switch on the bus and then turns on the first switch connected to the bus driver. If the fault is encountered after turning on the first switch, then it is determined that the fault was caused by either the first switch, a device connected to the bus as a result of turning on the first switch, or one of the bus connectors just switched on as a result of turning on the first switch. If the fault is not encountered, the next switch is turned on and the process is repeated until the fault is encountered. The fault when encountered will be caused by either the most recently turned on switch or a device or bus connectors switched in by the turning on of the last switch.

Abstract: A method, apparatus and program for dynamically allocating addresses to computer devices connected to Inter Integrated Circuit (I2C) buses are provided. Upon resetting a I2C bus, the invention uses a bus driver to turn on the first bus switch on the bus. The invention then accesses the first device downstream of the switch and allocates a new value to the device's address. The invention proceeds to turn on the next switch downstream. A new address is then allocated to the device downstream from the second switch. This process continues until all of the devices connected to the bus have unique addresses.

Abstract: A bus switch module for use in a bus such as an I2C bus is provided. In one embodiment, the switch module includes a control unit and a switch. The control unit includes an input for receiving instructions from a bus driver as to whether to close or open the switch. The switch includes a first and a second data connection which connect the switch to a first and a second segment of the bus and includes a control input for receiving commands from the control unit. The control unit opens and closes the switch in response to instructions received from the bus driver and signals received in the first data connection are passed to the second data connection only when the switch is closed in response to a command from the control unit.

Abstract: A debug card suitable for use with a data processing system is disclosed. The card includes a microcontroller, a storage device connected to the microcontroller; and, connected to the microcontroller, means for tapping into a communication bus of the data processing system where the bus communicates information between a processor of the data processing system and a display panel. The microcontroller is configured to record the information received by the display panel from the processor in the storage device when the debug card is connected to the communication bus. In one embodiment, the communication bus and the microcontroller are I2C compliant. In this embodiment, the debug card may have its own I2C address thereby enabling the debug card to communicate with the processor. The debug card may further include a serial port connected to the microcontroller. The serial port enables downloading the information stored in the storage device to an external computer.

Abstract: A method and apparatus for storing and using chipset built-in self-test (BIST) signatures is provided. A BIST for a chip in a data processing system may be initiated by a power-on-reset in the data processing system. The BIST signature generated during the BIST is compared with a predetermined BIST signature stored in a vital products data (VPD) module associated with the chip is read. A difference between the generated BIST signature and the predetermined BIST signature is then reported.

Abstract: A computer system including a central processing unit and a system memory accessible to the central processing unit via a host bus. A primary non-volatile storage element and a backup non-volatile storage element are incorporated into the system's motherboard. The primary non-volatile storage element contains the system's boot code that is executed following a reset or power on event. The backup non-volatile storage element contains a restoration sequence that is suitable for reprogramming a first portion of the boot code in the primary non-volatile storage element. A jumper block on the motherboard determines which of the non-volatile storage elements is initially addressed following a power on event. Preferably, the first portion of the boot code comprises the system's boot block or gold code and includes a sequence for downloading and reprogramming remaining portions of the boot code. The primary non-volatile storage element is preferably implemented as a multiple sector flash memory device.