Abstract: A pwm controller 10 which includes a Vcc node (pin 6); a start-up current source 180 connected to the Vcc node; and a driver circuit 150, 190 also connected to the Vcc node, wherein the pwm controller 10 is arranged to operate in a first phase in which the start-up current source supplies 180 current to the Vcc node but the driver circuit is turned off; a second phase in which the driver circuit 150,190 is enabled and draws current from the Vcc node; and a third phase in which both the start-up current source 180 and the driver circuit 150,190 are turned off whereby very little current may be drawn from the Vcc node (pin 6) during the third phase.

Abstract: A Pulse Width Modulation (PWM) control circuit is used in a switched-mode power supply (SMPS) having a normal mode and a standby mode, for controlling and regulating the SMPS. An input of the PWM control circuit is arranged to receive a signal indicating an amount of current supplied by the supply. An over-current determining arrangement provides an over-current signal in the event of there being an over-current condition in the signal indicating the amount of current supplied by the supply. A further input of the PWM control circuit receives a regulation signal in the event of there being a regulation output from circuitry coupled to receive power from the SMPS. A logic circuit within the PWM control circuit compares the over-current signal and the regulation signal in order to determine whether the switched-mode power supply is in standby mode or normal mode, thus avoiding the need for a dedicated control pin to indicate standby and normal modes.

Abstract: A power factor correction controller circuit 100 for controlling the duration of each on time phase and off time phase of a switched inductor power factor correction circuit 20, 30, 40, 50, 100 which is adapted for use with a rectifying arrangement 9, 10, 60, 70 producing a substantially regulated output voltage, Vo. The controller circuit 100 comprises an input terminal 114 for receiving a signal representative of Vo; an output terminal 131 for outputting a signal representative of the duration of each on time phase and off time phase; and on time determination means 110, 111, 112, 113, 114, 115, 116, 117; wherein the on time determination means acts to vary the maximum duration of each on time phase in an inverse dependence on Vo.

Abstract: A feedback circuit (10) for use with a feedback arrangement includes an input terminal (12) for receiving a feedback signal from an output of the feedback arrangement. An output terminal (14) is coupled to a regulating arrangement of the feedback arrangement. A sampling arrangement (16) is coupled to the input terminal for providing a delayed feedback signal. A further arrangement (18,20,22,24,26,28) is coupled to the output terminal (14) for comparing the feedback signal with the delayed feedback signal and with a predetermined reference signal, such that the further arrangement (18,20,22,24,26,28) disables the regulating arrangement if a certain relationship exists between the compared signals.