Abstract: A computing device apparatus facilitates use of a deep low power mode that includes powering off the device's CPU by including a software routine configured to be run by the CPU that effects saving to a non-volatile memory a state of the CPU and/or the device's peripherals before entering the deep low-power mode. The software routine can be configured to control this state storage in response to detecting a low power event, i.e., loss of power sufficient to run the CPU, or a software command to enter the deep low power mode to save power as part of an efficiency program. Then, upon wake up from the deep low power mode, the software routine is first run by the CPU to effect restoring from the non-volatile memory the state of the CPU and the peripherals before execution of a primary application for the central processing unit.

Abstract: A computing device apparatus facilitates use of a deep low power mode that includes powering off the device's CPU by including a software routine configured to be run by the CPU that effects saving to a non-volatile memory a state of the CPU and/or the device's peripherals before entering the deep low-power mode. The software routine can be configured to control this state storage in response to detecting a low power event, i.e., loss of power sufficient to run the CPU, or a software command to enter the deep low power mode to save power as part of an efficiency program. Then, upon wake up from the deep low power mode, the software routine is first run by the CPU to effect restoring from the non-volatile memory the state of the CPU and the peripherals before execution of a primary application for the central processing unit.

Abstract: The invention includes a successive approximation register, a digital-to-analog converter, a comparator and a control stage. The control stage initially sets the successive approximation register to a first digital value. The digital-to-analog converter converts the digital value stored in the successive approximation register to an analog value. The comparator compares the converted digital value with an analog input value. The control stage restricts subsequent analog-to-digital conversion for the analog input value to a search interval above or below the first digital value depending on whether the analog input value is greater or lower than the converted analog value of the first digital value.

Abstract: The invention includes a successive approximation register, a digital-to-analog converter, a comparator and a control stage. The control stage initially sets the successive approximation register to a first digital value. The digital-to-analog converter converts the digital value stored in the successive approximation register to an analog value. The comparator compares the converted digital value with an analog input value. The control stage restricts subsequent analog-to-digital conversion for the analog input value to a search interval above or below the first digital value depending on whether the analog input value is greater or lower than the converted analog value of the first digital value.

Abstract: The present invention is an electronic device comprising a counter driven by an input clock signal for counting clock cycles and providing most significant bits of a count. A clock signal generating stage provides a first set of phase shifted clock signals having m different phases. The electronic device determines n least significant bits of the count of the counter from the logic states of the first set of m phase shifted clock signals.

Abstract: The present invention is an electronic device comprising a counter driven by an input clock signal for counting clock cycles and providing a count. A clock signal generating stage provides a first set of phase shifted clock signals having m different phases. The electronic device determines n least significant bits of the count of the counter from the logic states of the first set of m phase shifted clock signals.

Abstract: An electronic device with a CPU configured to be switched from a low power mode into a higher power mode in response to an interrupt and an interrupt relay coupled between an interrupt generator and the CPU. A functional stage is coupled to the interrupt relay and functionally linked with the interrupt so as to be used during the second mode of the CPU. The interrupt relay relays the received interrupt to the CPU only after a time needed for the functional stage to settle. Power is saved because the CPU is not powered while waiting for the functional stage to settle.

Abstract: In order to develop a method and a system for arranging or sorting receivable channels that transport emitted data and/or content, in particular broadcast channels, in accordance with at least one arranging or sorting principle, in such a way that even with a plurality of receivable channels, a simple, intuitive, and useful principle for arranging or sorting those channels is adhered to, it is proposed that the channels be arranged and/or sorted in accordance with the duration and/or intensity of the employment or use of the information and/or content transported by the respective channel.

Abstract: Navigation system for a vehicle having locations (a, o) of different selectable groups stored in memories and having a device for measuring the distance between the selected destination (z) and the locations (a, o) for a selected group, with the ability to call up the locations (a, o) belonging to the selected group as a function of the measured distance from the location (z) and to reproduce them on a reproduction device. A useful selection of the reproduced destinations is obtained by a device for controlling the reproduction of locations (a) whose distance is less than a specific location limit (r).