Patents by Inventor Joffre F. Bernard
Joffre F. Bernard has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8373148Abstract: The present resistive memory device includes first and second electrodes. An active layer is situated between the first and second electrodes. The active layer with advantage has a thermal conductivity of 0.02 W/Kcm or less, and is surrounded by a body in contact with the layer, the body having a thermal conductivity of 0.01 W/Kcm or less.Type: GrantFiled: April 26, 2007Date of Patent: February 12, 2013Assignee: Spansion LLCInventors: Zhida Lan, Manuj Rathor, Joffre F. Bernard
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Gettering/stop layer for prevention of reduction of insulating oxide in metal-insulator-metal device
Patent number: 8093698Abstract: An electronic device includes a first electrode, a second electrode and an insulating layer between the first and second electrodes, which insulating layer may be susceptible to reduction by H2. A gettering layer is provided on and in contact with the first electrode, the gettering layer acting as a protective layer for substantially avoiding reduction of the insulating layer by capturing and immobilizing H2. A glue layer may be provided between the gettering layer and first electrode. An additional gettering layer may be provided on and in contact with the second electrode, and a glue layer may be provided between the second electrode and additional gettering layer.Type: GrantFiled: December 5, 2006Date of Patent: January 10, 2012Assignee: Spansion LLCInventors: Manuj Rathor, Matthew Buynoski, Joffre F. Bernard, Steven Avanzino, Suzette K. Pangrle -
Publication number: 20080265240Abstract: The present resistive memory device includes first and second electrodes. An active layer is situated between the first and second electrodes. The active layer with advantage has a thermal conductivity of 0.02 W/Kcm or less, and is surrounded by a body in contact with the layer, the body having a thermal conductivity of 0.01 W/Kcm or less.Type: ApplicationFiled: April 26, 2007Publication date: October 30, 2008Inventors: Zhida Lan, Manuj Rathor, Joffre F. Bernard
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Gettering/stop layer for prevention of reduction of insulating oxide in metal-insulator-metal device
Publication number: 20080130195Abstract: An electronic device includes a first electrode, a second electrode and an insulating layer between the first and second electrodes, which insulating layer may be susceptible to reduction by H2. A gettering layer is provided on and in contact with the first electrode, the gettering layer acting as a protective layer for substantially avoiding reduction of the insulating layer by capturing and immobilizing H2. A glue layer may be provided between the first layer and first electrode. An additional gettering layer may be provided on and in contact with the second electrode, and a glue layer may be provided between the second electrode and additional gettering layer.Type: ApplicationFiled: December 5, 2006Publication date: June 5, 2008Inventors: Manuj Rathor, Matthew Buynoski, Joffre F. Bernard, Steven Avanzino, Suzette K. Pangrle -
Patent number: 6811671Abstract: A method of fabricating a semiconductor device, having a reduced-oxygen Cu—Zn alloy thin film (30) electroplated on a Cu surface (20) by electroplating, using an electroplating apparatus, the Cu surface (20) in a unique chemical solution containing salts of zinc (Zn) and copper (Cu), their complexing agents, a pH adjuster, and surfactants; and annealing the electroplated Cu—Zn alloy thin film (30); and a semiconductor device thereby formed. The method controls the parameters of pH, temperature, and time in order to form a uniform reduced-oxygen Cu—Zn alloy thin film (30), having a controlled Zn content, for reducing electromigration on the Cu—Zn/Cu structure by decreasing the drift velocity therein which decreases the Cu migration rate in addition to decreasing the void formation rate, for improving device reliability, and for increasing corrosion resistance.Type: GrantFiled: February 22, 2002Date of Patent: November 2, 2004Assignee: Advanced Micro Devices, Inc.Inventors: Sergey Lopatin, Alexander H. Nickel, Joffre F. Bernard
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Patent number: 6770559Abstract: A conductive element of an integrated circuit wiring network is formed by a plating process. A seed layer for the conductive material is grown on the sidewalls and bottom surface of a trench using a low energy ion implantation process. The implantation is performed at an angle to the substrate to achieve coverage of the trench sidewalls. The resulting seed layer avoids constricting or closing the opening of the trench and has an approximately uniform thickness.Type: GrantFiled: October 29, 2002Date of Patent: August 3, 2004Assignee: Advanced Micro Devices, Inc.Inventors: Ercan Adem, Fei Wang, Joffre F. Bernard
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Publication number: 20030217462Abstract: The reliability and electromigration performance of planarized metallization patterns in an electrical device, for example copper, inlaid in the surface of a layer of dielectric material overlying a semiconductor substrate, are enhanced by a method for more reliably and uniformly diffusing into a conductive fill alloying elements which reduce or substantially prevent electromigration. The method comprises depositing around a conductive fill metal alloy films and alloying layers comprising one or more alloying elements having physical and/or chemical attributes which are effective for minimizing or substantially preventing electromigration along grain boundaries and/or along the interface between the surfaces of the conductive fill and other surfaces. The metal alloy films and alloying layers are advantageously deposited where their particular physical and/or chemical attributes may be most beneficial for improving electromigration performance.Type: ApplicationFiled: December 13, 2001Publication date: November 27, 2003Inventors: Fei Wang, Brian J. MacDonald, Amit P. Marathe, John E. Sanchez, Pin-Chin C. Wang, Joffre F. Bernard
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Patent number: 6630741Abstract: A method of reducing electromigration in a graded reduced-oxygen dual-inlaid copper interconnect line by filling a via with a graded Cu-rich Cu—Zn alloy fill electroplated on a Cu surface using a stable chemical solution, and by controlling and ordering the Zn-doping thereof, which also improves interconnect reliability and corrosion resistance, and a semiconductor device thereby formed. The method involves using a graded reduced-oxygen Cu—Zn alloy as fill for the via in forming the dual-inlaid interconnect structure. The graded alloy fill is formed by electroplating, while varying electroplating parameters, the Cu surface in a unique chemical solution containing salts of Zn and Cu, their complexing agents, a pH adjuster, and surfactants, thereby electroplating the graded fill on the Cu surface; and annealing the electroplated graded Cu—Zn alloy fill; and planarizing the Cu—Zn alloy fill, thereby forming the graded reduced-oxygen dual-inlaid copper interconnect line.Type: GrantFiled: December 7, 2001Date of Patent: October 7, 2003Assignee: Advanced Micro Devices, Inc.Inventors: Sergey Lopatin, Paul L. King, Joffre F. Bernard
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Patent number: 6624074Abstract: A method of fabricating a semiconductor device having contaminant-reduced Ca-doped Cu surfaces formed on Cu interconnects by cost-effectively depositing a Cu—Ca—X surface and subsequently removing the contaminant layer contained therein; and a device thereby formed. In the Cu—Ca—X surface, where contaminant X═C, S, and O, removal of the contaminant from such surface is achieved by (a) immersing the Cu interconnect surface into an electroless plating solution comprising Cu salts, Ca salts, their complexing agents, a reducing agent, a pH adjuster, and at least one surfactant for facilitating Ca-doping of the Cu interconnect material; and (b) annealing of the Cu—Ca—X surface under vacuum onto the underlying Cu interconnect material to form a Cu—Ca film on Cu interconnect structure, thereby producing a uniform Cu—Ca film (i.e., Cu-rich with 0.Type: GrantFiled: August 13, 2002Date of Patent: September 23, 2003Assignee: Advanced Micro Devices, Inc.Inventors: Sergey Lopatin, Joffre F. Bernard, Paul L. King
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Patent number: 6621165Abstract: A semiconductor device having contaminant-reduced calcium-copper (Ca—Cu) alloy surfaces formed on Cu interconnects fabricated by cost-effectively removing the contaminant layer.Type: GrantFiled: May 23, 2002Date of Patent: September 16, 2003Inventors: Sergey Lopatin, Paul L. King, Joffre F. Bernard
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Patent number: 6541860Abstract: An integrated circuit and a method for manufacture thereof are provided having a semiconductor substrate with a semiconductor device. A device dielectric layer is formed on the semiconductor substrate. An opening is formed in the dielectric layer. A barrier layer with an alloying element is deposited to line the opening in the dielectric layer. A conductor core is deposited on the barrier layer to fill the opening and connect to the semiconductor device. The conductor core is annealed causing migration of the alloy element into the conductor core.Type: GrantFiled: June 5, 2001Date of Patent: April 1, 2003Assignee: Advanced Micro Devices, Inc.Inventors: Christy Mei-Chu Woo, Pin-Chin Connie Wang, Joffre F. Bernard
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Patent number: 6541286Abstract: A method is provided for X-ray imaging and analyzing grain boundaries, nodules or extrusions, voids, and separations or delaminations in conductive layers under dielectric capping layers in integrated circuit interconnects.Type: GrantFiled: June 27, 2001Date of Patent: April 1, 2003Assignee: Advanced Micro Devices, Inc.Inventors: Joffre F. Bernard, Minh Quoc Tran
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Patent number: 6515367Abstract: An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A device dielectric layer is formed on the semiconductor substrate, and a channel dielectric layer formed on the device dielectric layer has an opening formed therein. A barrier layer lines the channel opening, and a conductor core fills the opening over the barrier layer. Self-aligned sub-caps of silicide and/or oxides are formed over the conductor core and then capped by a capping layer which covers the sub-caps and the channel dielectric layer.Type: GrantFiled: April 15, 2002Date of Patent: February 4, 2003Assignee: Advanced Micro Devices, Inc.Inventors: Joffre F. Bernard, Minh Van Ngo, Tim Z. Hossain
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Patent number: 6479898Abstract: An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A device dielectric layer formed on the semiconductor substrate. A channel dielectric layer on the device dielectric layer has an opening formed therein and a surface region of nitrogen. A barrier layer lines the channel opening and reacts with the nitrogen to form an improved metal nitride surfaced barrier layer. A conductor core fills the opening over the barrier layer.Type: GrantFiled: January 11, 2001Date of Patent: November 12, 2002Assignee: Advanced Micro Devices, Inc.Inventors: Dawn M. Hopper, Minh Van Ngo, Joffre F. Bernard
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Patent number: 6469387Abstract: A method of fabricating a semiconductor device having contaminant-reduced Ca-doped Cu surfaces formed on Cu interconnects by cost-effectively depositing a Cu—Ca—X surface and subsequently removing the contaminant layer contained therein; and a device thereby formed. In the Cu—Ca—X surface, where contaminant X=C, S, and O, removal of the contaminant from such surface is achieved by (a) immersing the Cu interconnect surface into an electroless plating solution comprising Cu salts, Ca salts, their complexing agents, a reducing agent, a pH adjuster, and at least one surfactant for facilitating Ca-doping of the Cu interconnect material; and (b) annealing of the Cu—Ca—X surface under vacuum onto the underlying Cu interconnect material to form a Cu—Ca film on Cu interconnect structure, thereby producing a uniform Cu—Ca film (i.e., Cu-rich with 0.Type: GrantFiled: November 30, 2000Date of Patent: October 22, 2002Assignee: Advanced Micro Devices, Inc.Inventors: Sergey Lopatin, Joffre F. Bernard, Paul L. King
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Patent number: 6465867Abstract: An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A device dielectric layer is formed on the semiconductor substrate. A channel dielectric layer on the device dielectric layer has an opening formed therein. A barrier layer, which has been implanted with a compounding material, lines the channel opening. A conductor core fills the opening over the barrier layer. The barrier layer having a dielectric layer proximate portion of a barrier compound varying into a conductor core proximate portion of a pure barrier material.Type: GrantFiled: February 21, 2001Date of Patent: October 15, 2002Assignee: Advanced Micro Devices, Inc.Inventors: Joffre F. Bernard, Sergey D. Lopatin
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Patent number: 6444580Abstract: A method of fabricating a semiconductor device having contaminant-reduced calcium-copper (Ca—Cu) alloy surfaces formed on Cu interconnects by cost-effectively removing the contaminant layer and a device thereby formed.Type: GrantFiled: November 30, 2000Date of Patent: September 3, 2002Assignee: Advanced Micro Devices, Inc.Inventors: Sergey Lopatin, Paul L. King, Joffre F. Bernard
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Patent number: 6406996Abstract: An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A device dielectric layer is formed on the semiconductor substrate, and a channel dielectric layer formed on the device dielectric layer has an opening formed therein. A barrier layer lines the channel opening, and a conductor core fills the opening over the barrier layer. Self-aligned sub-caps of silicide and/or oxides are formed over the conductor core and then capped by a capping layer which covers the sub-caps and the channel dielectric layer.Type: GrantFiled: September 30, 2000Date of Patent: June 18, 2002Assignee: Advanced Micro Devices, Inc.Inventors: Joffre F. Bernard, Minh Van Ngo, Tim Z. Hossain