Abstract: An exemplary embodiment includes a first binary counter whose counting period corresponds to a block length of a pulse frame, a block counter controlled by the first counter, and a logic element for generating working clock signals, wherein the counters are switchable for employment in different multiplex systems and the logic element gates out the working clock signals for different multiplex systems.

Abstract: A time division multiplex signal of a high order with a frame code word occurring as a block is distributed between a plurality of channels in a demultiplexer by way of a chain circuit of conductor elements. Further on the transmission path contains memories and a channel distributor. The channel distributor is controlled by a second memory by way of a decoder, other memories and a coder in a single step. A logic linking arrangement and a frame counter permit resynchronization only when the frame code word has failed to appear four times. The synchronous multiplexer facilitates high-speed operation at bit rates of 140 Mbit/s and 565 Mbit/s and likewise permits construction in accordance with emitter-coupled logic technology.

Abstract: The invention relates to an electrical filter circuit operated with a definite sampling and clock frequency f.sub.T, such filter being made up of CTD elements, and having at least one bipolar or quadripolar resonator in the form of a self-contained conductor loop (for example, C.sub.1, C.sub.2) with unidirectional transmission behavior.Differences in the transfer capacitances of such circuits are reduced, as far as possible, in order to thereby simplify integrated manufacture as far as possible, by positioning the frequency band to be filtered out at a frequency position which lies above half the clock frequency (f.sub.T /2), or in the range from f.sub.T /2 through 3f.sub.T /2.