Patents by Inventor Johannes Hubertus Antonius Brekelmans

Johannes Hubertus Antonius Brekelmans has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11522557
    Abstract: A digital conversion system including a sigma-delta converter, a tone generator that generates injects a tone signal into the conversion path of the sigma-delta converter at a frequency that is outside operating signal frequency range, a tone detector that isolates and detects a level of the injected tone signal and provides a corresponding tone level value, a tone ratio comparator that converts the tone level value into a tone level ratio and that compares the converted tone level ratio with an expected tone level ratio to provide an error signal, and a loop controller that converts the error signal to a correction signal to adjust a loop filter frequency the sigma-delta converter. Tones may be serially injected one at a time or simultaneously in parallel for determining a measured tone level ratio for comparison with a corresponding one of multiple stored expected tone level ratios.
    Type: Grant
    Filed: July 29, 2021
    Date of Patent: December 6, 2022
    Assignee: NXP B.V.
    Inventors: Robert Rutten, Martin Kessel, Hendrik van der Ploeg, Lucien Johannes Breems, Muhammed Bolatkale, Evert-Jan Pol, Manfred Zupke, Bernard Burdiek, Johannes Hubertus Antonius Brekelmans, Shagun Bajoria
  • Patent number: 11502699
    Abstract: A digital conversion system including a sigma-delta converter, a signal generator providing a substantially symmetrical injection signal that is injected into the sigma-delta converter conversion path, bandpass filters for filtering the injection signal and the output of the sigma-delta converter, a correlator that correlates the filtered signals for providing an error signal, and a loop controller that uses the error signal to adjust a resonant frequency of the sigma-delta converter to output a target notch frequency. The loop controller may adjust a resonant frequency of a loop filter of the sigma-delta converter, in which the bandpass filters may each be centered at the target notch frequency at the output of the sigma-delta converter. The correlator may include a complex conjugate block, a multiplier and a mean calculator. The loop controller may include a converter and an amplifier and an integrator or a least-mean square block.
    Type: Grant
    Filed: June 24, 2021
    Date of Patent: November 15, 2022
    Assignee: NXP B.V.
    Inventors: Robert Rutten, Hendrik van der Ploeg, Lucien Johannes Breems, Martin Kessel, Muhammed Bolatkale, Bernard Burdiek, Manfred Zupke, Johannes Hubertus Antonius Brekelmans, Shagun Bajoria
  • Patent number: 11038522
    Abstract: An apparatus including analog-to-digital conversion (ADC) circuitry is disclosed. The apparatus includes a plurality of comparators susceptible to offset variation and a shuffler circuit configured to shuffle input sources to the respective comparators. Feedback circuitry is also included and is configured and arranged with the ADC circuitry to detect offset variation in the outputs of each comparators for the shuffled inputs, relative to outputs of the plurality of comparators and compensate for the offset variation in the comparators based on the offset differences between the respective comparators.
    Type: Grant
    Filed: February 3, 2020
    Date of Patent: June 15, 2021
    Assignee: NXP B.V.
    Inventors: Johan Frederik Witte, Lucien Johannes Breems, Robert Rutten, Muhammed Bolatkale, Johannes Hubertus Antonius Brekelmans, Shagun Bajoria, Albertus Willibrordus Oude Essink
  • Patent number: 10541699
    Abstract: Aspects of the disclosure are directed to compensating for errors in in an analog-to-digital converter circuit (ADC). As may be implemented in accordance with one or more embodiments, an apparatus and/or method involves an ADC that converts an analog signal into a digital signal using an output from a digital-to-analog converter circuit (DAC). A compensation circuit generates a compensation output by, for respective signal portions provided to the DAC, generating a feedback signal based on an incompatibility between the conversion of the signal portions into an analog signal and the value of the signal portions provided to the DAC. A compensation output is generated based on the signal input to the DAC with a gain applied thereto, based on the feedback signal.
    Type: Grant
    Filed: October 11, 2018
    Date of Patent: January 21, 2020
    Assignee: NXP B.V.
    Inventors: Robert Rutten, Massimo Ciacci, Manfred Zupke, Lucien Johannes Breems, Johannes Hubertus Antonius Brekelmans, Muhammed Bolatkale, Shagun Bajoria, Soheil Bahrami
  • Patent number: 10098146
    Abstract: A processor is disclosed. The processor includes a first-receiver-node for receiving a first-receiver-signal, a second-receiver-node for receiving a second-receiver-signal, a first-output-node for coupling to a digital-baseband-processor, a second-output-node for coupling to the digital-baseband-processor and a first-active-data-pipe extending between the first-receiver-node and the first-output-node. The first-active-data-pipe includes a first-analog-to-digital-converter comprising a first-ADC-input coupled to the first-receiver-node and a first-ADC-output coupled to the first-output-node. The first-analog-to-digital-converter is configured to provide a first-digital-signal to the first-output-node. The processor comprises a first-reference-node and a configurable-data-pipe extending between the second-receiver-node and the second-output-node.
    Type: Grant
    Filed: November 18, 2016
    Date of Patent: October 9, 2018
    Assignee: NXP B.V.
    Inventors: Jan Niehof, Shagun Bajoria, Muhammed Bolatkale, Robert Rutten, Lucien Johannes Breems, Johannes Hubertus Antonius Brekelmans
  • Patent number: 9906384
    Abstract: Corrections are provided for mismatches between an in-phase (I) signal and a quadrature-phase (Q) signal, the I and Q signals having a first frequency band. A frequency filter circuit filters the I and Q signals to produce a filtered I and Q output with a second frequency band that is a subset of the first frequency band. Digital circuitry includes a multiple-tap correction filter having a plurality of taps and configured to generate I and Q output signals by filtering the I and Q signals according to respective sets of coefficients for the plurality of taps. A coefficient estimator generates the sets of coefficients relative to different frequency bands.
    Type: Grant
    Filed: September 26, 2016
    Date of Patent: February 27, 2018
    Assignee: NXP B.V.
    Inventors: Robert Rutten, Lucien Johannes Breems, Johannes Hubertus Antonius Brekelmans, Jan Niehof, Muhammed Bolatkale, Shagun Bajoria
  • Publication number: 20170150521
    Abstract: A processor is disclosed. The processor includes a first-receiver-node for receiving a first-receiver-signal, a second-receiver-node for receiving a second-receiver-signal, a first-output-node for coupling to a digital-baseband-processor, a second-output-node for coupling to the digital-baseband-processor and a first-active-data-pipe extending between the first-receiver-node and the first-output-node. The first-active-data-pipe includes a first-analogue-to-digital-converter comprising a first-ADC-input coupled to the first-receiver-node and a first-ADC-output coupled to the first-output-node. The first-analogue-to-digital-converter is configured to provide a first-digital-signal to the first-output-node. The processor comprises a first-reference-node and a configurable-data-pipe extending between the second-receiver-node and the second-output-node.
    Type: Application
    Filed: November 18, 2016
    Publication date: May 25, 2017
    Inventors: Jan Niehof, Shagun Bajoria, Muhammed Bolatkale, Robert Rutten, Lucien Johannes Breems, Johannes Hubertus Antonius Brekelmans
  • Patent number: 9419573
    Abstract: Embodiments of variable gain transimpedance amplifiers are described. In an embodiment, the variable gain transimpedance amplifier may include an amplifier coupled to an adjustable gain feedback network, the adjustable gain feedback network including a selectable set of Resistor-Capacitor (RC) branches, each RC branch having one or more unit RC elements, each unit RC element being comprised of a unit resistor and a unit capacitor arranged in parallel.
    Type: Grant
    Filed: June 27, 2014
    Date of Patent: August 16, 2016
    Assignee: NXP, B.V.
    Inventor: Johannes Hubertus Antonius Brekelmans
  • Patent number: 9413407
    Abstract: The invention relates to frequency conversion systems, in particular for use as up-converters or down-converters in radiofrequency (RF) receivers or transmitters, exemplary embodiments including a radiofrequency receiver including an RF signal input; a mixing module including a first plurality of IF amplifiers each connected to the RF signal input via a switch; a multi-phase local oscillator signal generator configured to provide a switching signal to each switch; and a summing module configured to receive output signals from each of the IF amplifiers and to provide a second plurality of output IF signals from a weighted sum of the IF amplifier output signals, wherein the second plurality is different to the first plurality.
    Type: Grant
    Filed: July 8, 2011
    Date of Patent: August 9, 2016
    Assignee: NXP B.V.
    Inventors: Jan van Sinderen, Johannes Hubertus Antonius Brekelmans, Frank Harald Erich Ho Chung Leong, Nenad Pavlovic
  • Publication number: 20150381129
    Abstract: Embodiments of variable gain transimpedance amplifiers are described. In an embodiment, the variable gain transimpedance amplifier may include an amplifier coupled to an adjustable gain feedback network, the adjustable gain feedback network including a selectable set of Resistor-Capacitor (RC) branches, each RC branch having one or more unit RC elements, each unit RC element being comprised of a unit resistor and a unit capacitor arranged in parallel.
    Type: Application
    Filed: June 27, 2014
    Publication date: December 31, 2015
    Applicant: NXP B.V.
    Inventor: Johannes Hubertus Antonius Brekelmans
  • Patent number: 8922288
    Abstract: An oscillator circuit comprising first and second resonator terminals for connecting to respective terminals of a resonator. The oscillator circuit also comprises a first inverting amplifier connected between the first and second resonator terminals in a first mode of operation; and a back to back pair of second inverting amplifiers connected between the first and second resonator terminals in a second mode of operation. There is also provided a controller configured to compare an operational parameter of the oscillator circuit to a switchover threshold, and switch the oscillator circuit from the first mode of operation to the second mode of operation when the operational parameter exceeds the switchover threshold.
    Type: Grant
    Filed: February 22, 2013
    Date of Patent: December 30, 2014
    Assignee: NXP, B.V.
    Inventors: Johannes Hubertus Antonius Brekelmans, Reinier Hoogendoorn, Nenad Pavlovic
  • Patent number: 8660508
    Abstract: An electronic device comprising a passive harmonic-rejection mixer (400) and a calibration circuitry (425). The passive harmonic rejection mixer has an input (102) connected to several sub-mixer stages (402), and the sub-mixer stages are connected to a summing module (406, 408) for generating the output (104). Each sub-mixing stage comprises a gating module (414), an amplifier (416), and a weighting module (418), the gating module selectively passing the input signal or the input signal with inverted polarity under the control of control signals. The calibration circuitry (425) is adapted to input a reference signal (430) to the input of the mixer, receive an output signal (104) from the output of the mixer, and set the weights (K1, K2, K3, K4) of the weighting modules to make the output signal match an expected output signal.
    Type: Grant
    Filed: April 23, 2010
    Date of Patent: February 25, 2014
    Assignee: NXP, B.V.
    Inventors: Dennis Jeurissen, Gerben Willem de Jong, Jan van Sinderen, Johannes Hubertus Antonius Brekelmans
  • Patent number: 8638174
    Abstract: The invention relates to a digital signal generator for providing one or more phases of a local oscillator signal for use in digital to analogue converters and harmonic rejection mixers. Embodiments disclosed include a local oscillator signal generator (200) for a mixer of a radiofrequency receiver, the signal generator (200) comprising a bit sequence generator (201) having a plurality of parallel output lines (203), a digital signal generator (202) having a serial output line (204) and a plurality of input lines connected to respective output lines (203) of the bit sequence generator (201) and a clock signal input line (205), wherein the digital signal generator (202) is configured to provide an output bit sequence on the serial output line (204) at a rate given by a clock signal provided on the clock signal input line (205) and a sequence given by a sequence of bits from the bit sequence generator (201) on the plurality of input lines (203).
    Type: Grant
    Filed: May 26, 2011
    Date of Patent: January 28, 2014
    Assignee: Integrated Device Technology inc.
    Inventors: Nenad Pavlovic, Johannes Hubertus Antonius Brekelmans, Jan van Sinderen
  • Patent number: 8378720
    Abstract: A signal processing arrangement comprises a series of latches (XDL, L1, L2) arranged as a clocked delay line (CDL) having a data input and a data output that are coupled to each other so as to form an inverting loop. An enable circuit (ACDL) allows or prevents a latch (L2) in the series of latches from changing state depending on whether, one clock cycle ago, the latch concerned received a given binary value or the inverse of that given binary 5 value, respectively, from the preceding latch (L1) in the series of latches. Such a circuit configuration allows a low-cost frequency division by an odd number with relatively small duty cycle errors.
    Type: Grant
    Filed: July 7, 2009
    Date of Patent: February 19, 2013
    Assignee: NXP B.V.
    Inventor: Johannes Hubertus Antonius Brekelmans
  • Patent number: 8354886
    Abstract: A signal processing arrangement comprises an amplifier (AMP V1) that includes a stage with complementary transistors (MP3, MN3) of opposite conductivity type arranged in series between two supply lines (+, ?). A controllable biasing circuit (CCS) is provided for changing a quiescent operating point of the stage as a function of a control signal (CS). A control arrangement measures an even order 5 distortion of the amplifier (AMP V1) and adjusts the control signal (CS) so that the even order distortion is below a critical level.
    Type: Grant
    Filed: August 10, 2009
    Date of Patent: January 15, 2013
    Assignee: NXP B.V.
    Inventor: Johannes Hubertus Antonius Brekelmans
  • Patent number: 8207878
    Abstract: A device for receiving a RF signal (1; 21) with loop-through output (16) is provided. The device comprises: an input (3) receiving a RF input signal (2); an analog-digital converter (8) converting the RF input signal (2) to a digital signal (9); a digital signal processing unit (10) digitally processing the digital signal (9); a digital-analog converter (14) converting the processed digital signal (13) to a loop-through RF signal (15) corresponding to the RF input signal (2); and a loop-through output (16) outputting the loop-through RF signal (15).
    Type: Grant
    Filed: November 24, 2008
    Date of Patent: June 26, 2012
    Assignee: NXP B.V.
    Inventors: Johannes Hubertus Antonius Brekelmans, Konstantinos Doris, Erwin Janssen
  • Patent number: 8203375
    Abstract: A frequency conversion circuit configured to mix a first input signal (RF+,RF?) at a first frequency with a second input signal (LO+,LO?) at a second frequency to provide an output intermediate frequency signal (IFout), the circuit comprising: first and second mixing modules, each mixing module comprising a voltage to current converter configured to receive the first input signal (RF+,RF?) and connected to a Gilbert mixer configured to receive the second input signal (LO+,LO?); an intermediate frequency output circuit having inputs connected to receive an intermediate frequency current signal (IF+,IF?) from outputs of each of the Gilbert mixers and an output configured to provide the output intermediate frequency voltage signal (IFout), wherein the first and second mixing modules comprise transistors which are complementary to each other.
    Type: Grant
    Filed: September 23, 2010
    Date of Patent: June 19, 2012
    Assignee: NXP B.V.
    Inventors: Gerben Willem de Jong, Johannes Hubertus Antonius Brekelmans
  • Publication number: 20120105128
    Abstract: An electronic device comprising a passive harmonic-rejection mixer (400) and a calibration circuitry (425). The passive harmonic rejection mixer has an input (102) connected to several sub-mixer stages (402), and the sub-mixer stages are connected to a summing module (406, 408) for generating the output (104). Each sub-mixing stage comprises a gating module (414), an amplifier (416), and a weighting module (418), the gating module selectively passing the input signal or the input signal with inverted polarity under the control of control signals. The calibration circuitry (425) is adapted to input a reference signal (430) to the input of the mixer, receive an output signal (104) from the output of the mixer, and set the weights (K1, K2, K3, K4) of the weighting modules to make the output signal match an expected output signal.
    Type: Application
    Filed: April 23, 2010
    Publication date: May 3, 2012
    Applicant: NXP B.V.
    Inventors: Dennis Jeurissen, Gerben Willem de Jong, Jan van Sinderen, Johannes Hubertus Antonius Brekelmans
  • Patent number: 8138817
    Abstract: An electronic device comprising a passive harmonic-rejection mixer. The passive harmonic rejection mixer has an input connected to several sub-mixer stages, and the sub-mixer stages are connected to a summing module for generating the output. Each sub-mixing stage comprises a gating module and a respective amplifier, the gating module adapted to selectively pass the input signal or the input signal with inverted polarity under the control of control signals.
    Type: Grant
    Filed: October 29, 2008
    Date of Patent: March 20, 2012
    Assignee: NXP B.V.
    Inventors: Johannes Hubertus Antonius Brekelmans, Gerben Willem De Jong, Rachid El Waffaoui, Dennis Jeurissen, Jan Van Sinderen, Simon W K Lee
  • Patent number: 8135375
    Abstract: A gain-controllable stage (CLN, A1, A2 . . . , A7, ACC) comprises a reactive signal divider (CLN) followed by an amplifier arrangement (A1, A2 . . . , A7, ACC). The reactive signal divider (CLN) may be in the form of, for example, a capacitive ladder network. The gain-controllable stage (CLN, A1, A2 . . . , A7, ACC) has a gain factor that depends on a signal division factor that the reactive signal divider (CLN) provides. The reactive signal divider (CLN) forms part of a filter (LC). The signal division factor is adjusted on the basis of a frequency (F) to which the receiver is tuned and a signal-strength indication (RS).
    Type: Grant
    Filed: August 23, 2006
    Date of Patent: March 13, 2012
    Assignee: NXP B.V.
    Inventor: Johannes Hubertus Antonius Brekelmans