Patents by Inventor Johannes M. van Meer
Johannes M. van Meer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11948832Abstract: A semiconductor manufacturing process and semiconductor device having an airgap to isolate bottom implant portions of a substrate from upper source and drain device structure to reduce bottom current leakage and parasitic capacitance with an improved scalability on n-to-p spacing scaling. The disclosed device can be implanted to fabricate nanosheet FET and other such semiconductor device. The airgap is formed by etching into the substrate, below a trench in a vertical and horizontal direction. The trench is then filled with dielectric and upper device structure formed on either side of the dielectric filler trench.Type: GrantFiled: September 21, 2021Date of Patent: April 2, 2024Assignee: Applied Materials, Inc.Inventors: Yan Zhang, Johannes M. van Meer, Naushad K. Variam
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Patent number: 11942361Abstract: Disclosed are approaches for forming semiconductor device cavities using directional dielectric deposition. One method may include providing a plurality of semiconductor structures and a plurality of trenches of a semiconductor device, and forming a dielectric atop the plurality of semiconductor structures by delivering a dielectric material at a non-zero angle of inclination relative to a normal extending perpendicular from a top surface of the plurality of semiconductor structures. The dielectric may be further formed by delivering the dielectric material at a second non-zero angle of inclination relative to the normal extending perpendicular from the top surface of the plurality of semiconductor structures.Type: GrantFiled: June 15, 2021Date of Patent: March 26, 2024Assignee: Applied Materials, Inc.Inventors: Armin Saeedi Vahdat, Tristan Y. Ma, Johannes M. van Meer, John Hautala, Naushad K. Variam
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Publication number: 20240049443Abstract: Approaches for reducing GIDL are disclosed. In one example, a method of forming a DRAM device may include forming a trench in a substrate layer, providing a first gate oxide layer along a sidewall and a bottom surface of the trench, and forming a first gate material within the trench. The method may further include removing the first gate oxide layer along an upper portion of the sidewall of the trench by delivering ions into the upper portion of the trench at a non-zero angle relative to a perpendicular extending from an upper surface of the substrate layer, and forming a second gate oxide layer along the upper portion of the sidewall of the trench, wherein a first dielectric constant of the first gate oxide layer is greater than a second dielectric constant of the second gate oxide layer.Type: ApplicationFiled: August 5, 2022Publication date: February 8, 2024Applicant: Applied Materials, Inc.Inventors: Armin Saeedi Vahdat, John Hautala, Yan Zhang, Johannes M. van Meer
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Publication number: 20230369453Abstract: A method for forming a nanosheet device. The method may include providing a heterostructure device stack above a semiconductor substrate. The method may include patterning the heterostructure device stack to define a dummy gate region, and before forming a source drain recess adjacent the dummy gate region, selectively removing a first set of sacrificial layers of the heterostructure device stack within the dummy gate region.Type: ApplicationFiled: May 13, 2022Publication date: November 16, 2023Applicant: Applied Materials, Inc.Inventors: Yan Zhang, Johannes M. van Meer, Sankuei Lin, Baonian Guo, Naushad K. Variam
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Patent number: 11778832Abstract: Disclosed are approaches for 3D NAND structure fabrication. One method may include providing a stack of layers comprising a first and second plurality of layers, and forming a plurality of trenches in the stack of layers, wherein each of the trenches includes a tiered sidewall. A first trench may be formed to a first depth, and a second trench may be formed to a second depth, which is greater than the first depth. The method may further include forming a liner within the trenches, wherein the liner is deposited at a non-zero angle of inclination relative to a normal extending perpendicular from the top surface of the stack of layers. The liner may have a first thickness along the tiered sidewall of the first trench and a second thickness along the tiered sidewall of the second trench, wherein the first thickness is greater than the second thickness.Type: GrantFiled: May 3, 2021Date of Patent: October 3, 2023Assignee: Applied Materials, Inc.Inventors: Armin Saeedi Vahdat, Tristan Y. Ma, Johannes M. van Meer, John Hautala, Naushad K. Variam
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Publication number: 20230187210Abstract: Approaches herein provide devices and methods for forming optimized gate-all-around transistors. One method may include forming a well by directing a first ion species into a substrate of a device, forming a plurality of alternating first and second layers over the well, and forming a dummy gate and a spacer over the plurality of alternating first and second layers. The method may further include removing a portion of the plurality of alternating first and second layers to expose an upper surface of the well, forming a punch through stopper in the well by directing a second ion species into the exposed upper surface of the well, etching the plurality of nanosheets to laterally recess the second layers relative to the first layers, and forming an inner spacer along the first and second layers.Type: ApplicationFiled: December 10, 2021Publication date: June 15, 2023Applicant: Applied Materials, Inc.Inventors: Yan Zhang, Johannes M. van Meer, Naushad K. Variam
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Publication number: 20230119618Abstract: A semiconductor manufacturing process and semiconductor device having an airgap to isolate bottom implant portions of a substrate from upper source and drain device structure to reduce bottom current leakage and parasitic capacitance with an improved scalability on n-to-p spacing scaling. The disclosed device can be implanted to fabricate nanosheet FET and other such semiconductor device. The airgap is formed by etching into the substrate, below a trench in a vertical and horizontal direction. The trench is then filled with dielectric and upper device structure formed on either side of the dielectric filler trench.Type: ApplicationFiled: October 15, 2021Publication date: April 20, 2023Applicant: Applied Materials, Inc.Inventors: Armin Saeedi Vahdat, John Hautala, Johannes M. van Meer
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Patent number: 11626284Abstract: A method to form a 2-Dimensional transistor channel may include depositing an amorphous layer comprising a 2-dimensional material, implanting an implant species into the amorphous layer; and annealing the amorphous layer after the implanting. As such, the amorphous layer may form a doped crystalline layer.Type: GrantFiled: January 15, 2021Date of Patent: April 11, 2023Assignee: Applied Materials, Inc.Inventors: Keith T. Wong, Hurshvardhan Srivastava, Srinivas D. Nemani, Johannes M. van Meer, Rajesh Prasad
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Publication number: 20230089482Abstract: A semiconductor manufacturing process and semiconductor device having an airgap to isolate bottom implant portions of a substrate from upper source and drain device structure to reduce bottom current leakage and parasitic capacitance with an improved scalability on n-to-p spacing scaling. The disclosed device can be implanted to fabricate nanosheet FET and other such semiconductor device. The airgap is formed by etching into the substrate, below a trench in a vertical and horizontal direction. The trench is then filled with dielectric and upper device structure formed on either side of the dielectric filler trench.Type: ApplicationFiled: September 21, 2021Publication date: March 23, 2023Applicant: Applied Materials, Inc.Inventors: Yan Zhang, Johannes M. van Meer, Naushad K. Variam
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Publication number: 20220399225Abstract: Disclosed are approaches for forming semiconductor device cavities using directional dielectric deposition. One method may include providing a plurality of semiconductor structures and a plurality of trenches of a semiconductor device, and forming a dielectric atop the plurality of semiconductor structures by delivering a dielectric material at a non-zero angle of inclination relative to a normal extending perpendicular from a top surface of the plurality of semiconductor structures. The dielectric may be further formed by delivering the dielectric material at a second non-zero angle of inclination relative to the normal extending perpendicular from the top surface of the plurality of semiconductor structures.Type: ApplicationFiled: June 15, 2021Publication date: December 15, 2022Applicant: Applied Materials, Inc.Inventors: Armin Saeedi Vahdat, Tristan Y. Ma, Johannes M. van Meer, John Hautala, Naushad K. Variam
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Publication number: 20220352182Abstract: Disclosed are approaches for 3D NAND structure fabrication. One method may include providing a stack of layers comprising a first and second plurality of layers, and forming a plurality of trenches in the stack of layers, wherein each of the trenches includes a tiered sidewall. A first trench may be formed to a first depth, and a second trench may be formed to a second depth, which is greater than the first depth. The method may further include forming a liner within the trenches, wherein the liner is deposited at a non-zero angle of inclination relative to a normal extending perpendicular from the top surface of the stack of layers. The liner may have a first thickness along the tiered sidewall of the first trench and a second thickness along the tiered sidewall of the second trench, wherein the first thickness is greater than the second thickness.Type: ApplicationFiled: May 3, 2021Publication date: November 3, 2022Applicant: Applied Materials, Inc.Inventors: Armin Saeedi Vahdat, Tristan Y. Ma, Johannes M. van Meer, John Hautala, Naushad K. Variam
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Patent number: 11424164Abstract: In one embodiment, a method may include providing a substrate, comprising a plurality of surface features, an isolation layer, disposed between the plurality of surface features, and a substrate base, disposed subjacent the isolation layer and the plurality of surface features, wherein the plurality of surface features extend above a surface of the isolation layer. The method may include directing a low energy ion beam to the substrate, when the substrate is heated at a targeted temperature, wherein an altered layer is formed within an outer portion of the isolation layer, and wherein an inner portion of the isolation layer is not implanted.Type: GrantFiled: August 28, 2020Date of Patent: August 23, 2022Assignee: Applied Materials, Inc.Inventors: Andrew Michael Waite, Johannes M. van Meer, Jae Young Lee
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Publication number: 20220108886Abstract: A method to form a 2-Dimensional transistor channel may include depositing an amorphous layer comprising a 2-dimensional material, implanting an implant species into the amorphous layer; and annealing the amorphous layer after the implanting. As such, the amorphous layer may form a doped crystalline layer.Type: ApplicationFiled: January 15, 2021Publication date: April 7, 2022Applicant: Applied Materials, Inc.Inventors: Keith T. Wong, Hurshvardhan Srivastava, Srinivas D. Nemani, Johannes M. van Meer, Rajesh Prasad
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Publication number: 20220068715Abstract: In one embodiment, a method may include providing a substrate, comprising a plurality of surface features, an isolation layer, disposed between the plurality of surface features, and a substrate base, disposed subjacent the isolation layer and the plurality of surface features, wherein the plurality of surface features extend above a surface of the isolation layer. The method may include directing a low energy ion beam to the substrate, when the substrate is heated at a targeted temperature, wherein an altered layer is formed within an outer portion of the isolation layer, and wherein an inner portion of the isolation layer is not implanted.Type: ApplicationFiled: August 28, 2020Publication date: March 3, 2022Applicant: Applied Materials, Inc.Inventors: Andrew Michael Waite, Johannes M. van Meer, Jae Young Lee
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Patent number: 11205593Abstract: Disclosed are approaches for forming finFET devices having asymmetric fins achieved via fin trimming. In some embodiments, a method may include providing a substrate within a process chamber, the substrate including a plurality of fins, and forming a capping layer over the plurality of fins, wherein the capping layer extends along a first sidewall and a second sidewall of each of the plurality of fins. The method may further include removing a portion of the capping layer to expose a target area of the first sidewall of each of the plurality of fins, and trimming the target area of the first sidewall of each of the plurality of fins to reduce a lateral width of an upper section of each of the plurality of fins.Type: GrantFiled: May 20, 2020Date of Patent: December 21, 2021Assignee: Applied Materials, Inc.Inventors: Min Gyu Sung, Johannes M. van Meer
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Publication number: 20210366776Abstract: Disclosed are approaches for forming finFET devices having asymmetric fins achieved via fin trimming. In some embodiments, a method may include providing a substrate within a process chamber, the substrate including a plurality of fins, and forming a capping layer over the plurality of fins, wherein the capping layer extends along a first sidewall and a second sidewall of each of the plurality of fins. The method may further include removing a portion of the capping layer to expose a target area of the first sidewall of each of the plurality of fins, and trimming the target area of the first sidewall of each of the plurality of fins to reduce a lateral width of an upper section of each of the plurality of fins.Type: ApplicationFiled: May 20, 2020Publication date: November 25, 2021Applicant: Applied Materials, Inc.Inventors: Min Gyu Sung, Johannes M. van Meer
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Publication number: 20210119022Abstract: Methods for forming semiconductor devices herein may include providing a metal gate, an interlayer dielectric (ILD), and an etch stop layer over a plurality of fins, wherein the ILD is formed atop the etch stop layer, and wherein the plurality of fins includes a source/drain (S/D) epitaxial region. The method may further include removing the etch stop layer from atop the S/D epitaxial region, and performing, through an opening in the ILD, an ion implant and a dopant ion implant to the S/D epitaxial region. In some embodiments, the method may further include thermally treating the semiconductor device to activate ions of the ion implant or ions of the dopant ion implant in the S/D epitaxial region to form an ultra-shallow junction.Type: ApplicationFiled: October 22, 2019Publication date: April 22, 2021Applicant: APPLIED Materials, Inc.Inventors: Jae Young Lee, Johannes M. Van Meer, Naushad K. Variam
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Patent number: 10269663Abstract: An apparatus of a wafer processing apparatus includes at least one memory and logic, at least a portion of which is implemented in circuitry of the wafer processing apparatus including at least one processor coupled to the at least one memory. The logic may provide a 3D model of a surface of a wafer, the wafer defining a wafer plane; and modify a surface feature in a Z-direction along the surface of the wafer based on at least one of: an X-critical dimension (CD) extending along an X-direction of the wafer plane, and a Y-CD extending along a Y direction of the wafer plane.Type: GrantFiled: January 6, 2017Date of Patent: April 23, 2019Assignee: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.Inventors: Morgan D. Evans, Tristan Ma, Kevin Anglin, Motoya Okazaki, Johannes M. van Meer
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Patent number: 10090166Abstract: A method may include performing a chemical mechanical polishing (CMP) etch of a fin assembly disposed on a substrate, the fin assembly comprising a plurality of fin structures coated with an oxide layer, wherein as a result of the CMP etch, a first portion of the oxide layer is removed, and the fin structures remain covered with oxide. The method may further include performing a selective area processing (SAP) etch using ions, wherein a second portion of the oxide layer is removed in a non-uniform manner, wherein after the SAP etch, the fin structures remain covered with oxide.Type: GrantFiled: January 6, 2017Date of Patent: October 2, 2018Assignee: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.Inventors: Andrew Michael Waite, Morgan D. Evans, Johannes M. van Meer, Jae Young Lee
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Publication number: 20180197747Abstract: A method may include performing a chemical mechanical polishing (CMP) etch of a fin assembly disposed on a substrate, the fin assembly comprising a plurality of fin structures coated with an oxide layer, wherein as a result of the CMP etch, a first portion of the oxide layer is removed, and the fin structures remain covered with oxide. The method may further include performing a selective area processing (SAP) etch using ions, wherein a second portion of the oxide layer is removed in a non-uniform manner, wherein after the SAP etch, the fin structures remain covered with oxide.Type: ApplicationFiled: January 6, 2017Publication date: July 12, 2018Inventors: Andrew Michael Waite, Morgan D. Evans, Johannes M. van Meer, Jae Young Lee