Abstract: A device for reading magnetic information, having at least one read head including at least one magnetoresistive bar MR for generating data pulses representative of information read by the head. To enable the bar to be biased accurately without requiring a measurement of the quiescent resistance of the bar, the device includes a control loop for controlling the power dissipated in the magnetoresistive bar, the control loop having a time constant which is large with respect to the duration of the data pulses.

Abstract: An arrangement for reading information from a record carrier, such as in a HDD, include a read head (Rmr1), an amplifier (74) for amplifying the signal read by the read head, an equalizer (76) for equalizing the signal read by the read head, and a bit detector (80) for detecting bits in the signal read by the read head. The invention, the arrangement further comprises a DC correction unit (78) for subtracting a correction value from an input signal in response to an error signal so as to obtain a DC corrected output signal. The bit detector (80) detects a sequence of bits based in the DC corrected output signal. Further, an error signal generating unit (82,83,85) is present for generating the error signal in response to the DC corrected output signal and the sequence.

Abstract: A recording apparatus for recording an information signal on a magnetic record carrier includes a write driver circuit and a magnetic write head. The write driver circuit comprises a first voltage driver and a second voltage driver. A first current driver and a second current driver are present for driving the write head. The first and second voltage driver each include a respective series circuit of an npn transistor and a bidirectional impedance element coupled between a point of constant potential and the respective outputs of the first and second voltage drivers.

Abstract: An arrangement is disclosed for reading information from a record carrier. The arrangement comprises a read head having at least one magneto-resistive element (Rmr), a first transistor (Tr1) and a second transistor (Tr2). The base of the first transistor (Tr1) is coupled to the emitter of the second transistor (Tr2) via a first capacitor (6). The base of the second transistor (Tr2) is coupled to the emitter of the first transistor (Tr1) via a second capacitor (8). The arrangement further comprises a non-linear transconductance amplifier (14) having first and second inputs coupled to the output terminals (10,12) of the arrangement, and having and inverting and non-inverting outputs coupled to the bases of the first and second transistor.

Abstract: A device for write precompensation of data signals to be recorded on a magnetic medium, has an input for receiving input data signals and an output for supplying the output signals to be recorded, at least a plurality of the signal transitions in these output data signals being delayed with respect to the corresponding signal transitions in the input data signal, the signal path between the input and the output including a series arrangement of a filter circuit and a hysteresis circuit, the hysteresis circuit receiving the output signal of the filter circuit and supplying a binary signal as its output signal. This write precompensation device simply enables allowance to be made for the influence of a large number of preceding symbol values on a transition to be recorded. When the device is combined with a known write compensation device it suffices to use a simple filter.

Abstract: An apparatus for detecting peaks of positive and negative polarity in an information signal. The apparatus comprises a first peak detector means for detecting the positive peaks and a second peak detector for detecting the negative peaks. The first peak detector means comprises a first capacitor, and has an attack time for charging the first capacitor (32) and a decay time for discharging the first capacitor, the attack time being shorter than the decay time. The first peak detector has an output for generating an output signal (42) having a first output signal value when the first peak detector is in a charging state for charging the first capacitor and having a second output value when the first peak detector is in a non-charging state.

Abstract: An automatic gain control circuit, for amplifying an input signal so that it has a specific correspondence with a reference value (V.sub.ref), includes an input terminal (2) for receiving the input signal, a variable gain amplifier (4) for amplifying the input signal in response to a gain control signal, a peak detector (14) for detecting peaks in the amplified input signal, the peak detector (14) having an attack time constant (T.sub.a) and a decay time constant (T.sub.d), and supplying a peak detector output signal (V.sub.p) representative of the amplitude of the peaks in the amplified input signal, a comparator (20) for comparing the peak detector output signal (V.sub.p) with the reference value (V.sub.ref) to form an error signal (e), and an integrator (30) for integrating the error signal (e) to form the gain control signal.

Abstract: A method and a device in which information is written on a medium and is read out, and which establishes whether the information read is sufficiently reliable, and in which so-called erasure information is used to establish the influence of media defects and other imperfections on the occurrence of errors in a transmission system. The medium is, for example, a hard disk containing one or more bad spots whose location can be accurately detected. The implementation of the method makes accurate and fast computation of the bit error rate possible.

Abstract: A fast acquisition method is described that combines timing, gain and, if required, equalizer acquisition in one go with word synchronization. At the heart of the method is a preamble that begins with a repetition of identical words P whose length matches the code-word length. Preferably the method ends with a frame-sync word based on the bit-by-bit inverse of P. Main attractions of the technique are simplicity, speed, and robustness.

Abstract: A device for write precompensation of data signals to be recorded on a magnetic medium, which device has an input for receiving input data signals and an output for supplying output signals to be recorded, an integrator/limiter circuit which receives the input data signals and which supplies an output signal which is in synchronism with the data signal and whose amplitude varies substantially linearly as a function of time at positions where a signal transition appears in the data signal, which amplitude is limited within a data symbol interval; an adjustable filter which receives the input signals and supplies an output signal whose instantaneous values depend on the pattern of preceding and future signal transitions in the data signal; and a comparator circuit which through comparison of the output signal of the integrator/limiter circuit and the output signal of the filter produces the output signal in which at least some signal transitions of the input data signal can be shifted in time.

Abstract: An unreliability detector apparatus for generating an unreliable decision signal in response to an input signal. An input terminal receives the input signal, a first comparator unit compares the input signal with a first threshold value and a second comparator unit compares the input signal with a second threshold value. A processor is provided for carrying out a function for determining whether a curve in an X-Y plane has at least one point in common with a predetermined line in the X-Y plane. The curve in the X-Y plane is obtained by plotting time equivalent signals values of the first and second comparator output signals along the Y- and X-axis respectively of the X-Y plane, while the predetermined line in the X-Y plane is formed by a first line interconnecting a first fixed point and a second fixed point and in which half plane a third fixed point is located. The three fixed points are obtained by plotting combinations of a first through a fourth signal value along the X- and Y-axis.

Abstract: Control circuit for generating two control currents for a variable gain amplifier having a gain which is substantially proportional to the ratio of the two control currents. For a gain control which is independent of the signal level of the variable gain amplifier an exponential control characteristic is needed. The control circuit generates a set of control currents 2*I and 2*J with a ratio which is pseudo-exponential dependent on the control parameter u.sub.c. The ideal exponential characteristic is approximated to with a second-order function of the type ((1+x)/(1-x)).sup.2 by means of a voltage-to-current converter, a first translinear loop and a second translinear loop.

Abstract: A digital information signal is channel encoded into a channel signal. Data sequences in the channel encoded information signal that give rise to an analog signal, upon reproduction or reception, with a single frequency component at f.sub.b M, are limited in length. M being an integer constant larger than 2 and f.sub.b being the bit frequency in the channel encoded information signal.

Abstract: An electronic circuit comprises coupled transconductors (TR1 and TR2). The transconductors comprise two complementary differential pairs whose outputs are connected directly to two output terminals. Two diodes (P3, N3) are arranged in series between the common terminals of the differential pairs. The common-mode voltage of the differential pairs is available on the node between the two diodes. The common-mode voltage of the one transconductor (TR2) is used to control one of the bias current sources of the other transconductor (TR1) and, if desired, also that of the one transconductor (TR2). In this way the common-mode voltage on the output terminals of the other transconductor (TR1) is fixed.

Abstract: A recording apparatus including a magnetic write head and a write amplifier with capacitive current compensation. The write amplifier is made up of four current mirrors which are turned on two at a time by two switchable floating current sources connected between the input terminals of the current mirrors in order to produce a write current of alternating polarity through the write head. The parasitic capacitances across the write head and/or the parasitic capacitances of the write amplifier at the write terminals are neutralized by means of neutralizing capacitors. The high impedance at the terminals of the write head enables the common-mode voltage across the write head to be fixed at any desired voltage value by means of a common-mode circuit.

Abstract: An apparatus for recording on a magnetic record carrier includes a write amplifier comprising four current mirrors which are turned on two at a time by two switchable floating current sources connected between the input terminals of the current mirrors in order to produce a write current of alternating polarity through a write head. The high impedance at the terminals of the write head enables the common-mode voltage across the write head to be fixed at any desired voltage value by means of a common-mode circuit. The symmetrical structure further enables the parasitic capacitances at the write terminals to be neutralized by means of neutralizing capacitors.

Abstract: An arrangement for reading out an information signal from a magnetic record carrier. The arrangement includes a read head having a magneto-resistive (MR) element (R.sub.m1) with a first terminal (3) connected to a first point (13) of constant potential, and a second terminal (4); a bias-current generator (2) having an output (5) for supplying a bias-current to the MR element; and an amplifier circuit (1) having a first terminal (6) coupled to the output (5) of the bias-current generator (2), and a second terminal (7) coupled to the second terminal (4) of the magneto-resistive element (R.sub.m1) so as to form a series arrangement of the bias-current generator, the amplifier circuit and the magneto-resistive element. At an output terminal (8), the information signal is available. The amplifier circuit (1) includes a MOS transistor T.sub.1 coupled between the output terminal (8) and the second terminal (7), and a feedback circuit, including a resistor (R.sub.1) and a capacitor (C.sub.

Abstract: A preamplifier circuit for a computer data storage system disk drive read/write head (or HSA) includes multiple test modes to enable electrical testing of the preamplifier, the read/write heads, and associated circuitry without physically probing the components or circuitry. Communication between the preamplifier and a host controller provides for test mode selection and test mode enablement within the preamplifier. Testing occurs using only the normal interface connector to the head disk assembly (HDA) in which the preamplifier and HSA are embodied. Properties such as electrical resistance, ESD, preamplifier bond wire connection integrity, head bond wire and solder joint integrity, and connections from the head slider to the preamplifier leads are all tested. Testing occurs without probing to provide efficient, reliable, and cost effective manufacturing and testing benefits of the read/write heads, flex assembly, HSA, and HDA.

Abstract: A differential amplifier with common-mode rejection for low supply voltages has a first and a second differential pair without transistors in the tails of the differential pairs and with proportional common-mode currents flowing through the first and the second differential pair. The differential amplifier includes a current mirror which feeds the common-mode current of the second differential pair (3, 4) back to the output terminals of the first differential pair for the rejection of common-mode currents at the output terminals. The voltage at the output terminals of the current mirror has a d.c. level which can be established by means of a first reference voltage source independently of the common-mode voltage at the input terminals of the differential amplifier.

Abstract: An arrangement for reading out an information signal from a magnetic record carrier. The arrangement includes a read head having a magneto-resistive element with a first terminal connected to a first point of constant potential, and a second terminal; a bias-current generator having an output for supplying a bias-current to the MR element and an amplifier circuit having a first terminal coupled to the output of the bias-current generator, and a second terminal coupled to the second terminal of the MR so as to form a series arrangement of the bias-current generator, the amplifier circuit and the MR element. At an output terminal of the amplifier circuit, the information signal is available.