Abstract: The present invention relates to a method of selectively removing metal oxide, particularly tungsten oxide without etching the un-oxidized metal. The method removes metal oxide with little or no loss of the clean metal to improve the contact resistance for contact metal in semiconductor device fabrication. The method includes a step of exposing a substrate containing a tungsten oxide layer over a tungsten layer to a low oxygen aqueous ammonia solution to selectively remove the tungsten oxide layer. The low oxygen aqueous ammonia solution has an ammonia concentration in a range of about 0.01 M to about 2.0 M. The oxygen level in the solution is no more than 50 ppb. The solution may further contain a corrosion inhibitor and/or a compound having two or more carboxyl groups separated by at least one carbon atom.

Abstract: Ions depleted from a chemical bath by a reaction such as plating are continually replenished by production and moving of ions through selectively permeable membranes while isolating potential contaminant ions from the chemical bath.

Abstract: A method of forming an interconnect structure in an inter-layer dielectric (ILD) material, the method include the steps of creating one or more via openings in the ILD material; forming a first liner covering at least one of the one or more via openings; creating one or more trench openings on top of at least one of the one or more via openings covered by the first liner; and forming a second liner covering the trenching openings and at least part of the first liner. An interconnect structure formed by the method is also provided.

Abstract: Disclosed is a method of making a semiconductor structure, wherein the method includes forming an interlayer dielectric (ILD) layer on a semiconductor layer, forming a conductive plating enhancement layer (PEL) on the ILD, patterning the ILD and PEL, depositing a seed layer into the pattern formed by the ILD and PEL, and then plating copper on the seed layer. The PEL serves to decrease the resistance across the wafer so to facilitate the plating of the copper. The PEL preferably is an optically transparent and conductive layer.

Abstract: A method of forming an interconnect structure in an inter-layer dielectric (ILD) material, the method include the steps of creating one or more via openings in the ILD material; forming a first liner covering at least one of the one or more via openings; creating one or more trench openings on top of at least one of the one or more via openings covered by the first liner; and forming a second liner covering the trenching openings and at least part of the first liner. An interconnect structure formed by the method is also provided.

Abstract: A semiconductor device containing a diffusion barrier layer is provided. The semiconductor device includes at least a semiconductor substrate containing conductive metal elements; and, a diffusion barrier layer applied to at least a portion of the substrate in contact with the conductive metal elements, the diffusion barrier layer having an upper surface and a lower surface and a central portion, and being formed from silicon, carbon, nitrogen and hydrogen with the nitrogen being non-uniformly distributed throughout the diffusion barrier layer. Thus, the nitrogen is more concentrated near the lower and upper surfaces of the diffusion barrier layer as compared to the central portion of the diffusion barrier layer. Methods for making the semiconductor devices are also provided.

Abstract: A diffusion barrier that has a low dielectric constant, k, yet resistant to oxygen and/or moisture permeability is provided. The diffusion barrier includes a dielectric stack having at least two or more dielectric films, each film having a dielectric constant of about 8 or less, wherein the dielectric stack comprises alternating films composed of a high-permeability material and a low-permeability material. A semiconductor structure including substrate having at least one wiring region and the inventive diffusion barrier formed on a surface of the substrate is also provided.

Abstract: A metal plus low dielectric constant (low-k) interconnect structure is provided for a semiconductor device wherein adjacent regions in a surface separated by a dielectric have dimensions in width and spacing in the sub 250 nanometer range, and in which reduced lateral leakage current between adjacent metal lines, and a lower effective dielectric constant than a conventional structure, is achieved by the positioning of a differentiating or mask member that is applied for the protection of the dielectric in subsequent processing operations, at a position about 2-5 nanometers below a, to be planarized, surface where there will be a lower electric field.

Abstract: A metal plus low dielectric constant (low-k) interconnect structure is provided for a semiconductor device wherein adjacent regions in a surface separated by a dielectric have dimensions in width and spacing in the sub 250 nanometer range, and in which reduced lateral leakage current between adjacent metal lines, and a lower effective dielectric constant than a conventional structure, is achieved by the positioning of a differentiating or mask member that is applied for the protection of the dielectric in subsequent processing operations, at a position about 2-5 nanometers below a, to be planarized, surface where there will be a lower electric field.

Abstract: An over voltage spike or surge protection principle is provided that involves an element that is positioned between a node in the circuitry and a reference voltage that performs as an insulator as voltage across the element increases and at a selectable voltage, the current at any higher voltage such as during a spike or a surge is shunted to reference or ground, the element is not damaged by the breakdown type of the effect of the shunting of the current, and then, after the duration of the high voltage excursion the element returns to the performance before the selectable voltage. The principle of the invention permits in-situ or locallized over voltage protection to selected nodes throughout circuitry as well as throughout an integrated circuit including the interface with external circuitry.

Abstract: A diffusion barrier that has a low dielectric constant, k, yet resistant to oxygen and/or moisture permeability is provided. The diffusion barrier includes a dielectric stack having at least two or more dielectric films, each film having a dielectric constant of about 8 or less, wherein the dielectric stack comprises alternating films composed of a high-permeability material and a low-permeability material. A semiconductor structure including substrate having at least one wiring region and the inventive diffusion barrier formed on a surface of the substrate is also provided.