Abstract: The invention relates to transconductor circuits, particularly but not exclusively to a single-ended transconductor circuit (50), balanced transconductor circuits and a filter suitable for use in a wireless transceiver. The single-ended transconductor (50) comprises an inverter (51) having an input (54) and an output (55). A resistive element (58) is connected between the input (54) and the output (55).

Abstract: A transconductor circuit, such as a gyrator filter, comprises an arrangement of balanced class AB transconductors, capacitors and floating MOS resistors formed by MOS transistors operating in their triode region. Tuning of the filter is effected by varying a common supply rail voltage. The circuit includes a means for producing a voltage offset from the common mode voltage of the class AB transconductors. The offset voltage is supplied to a parallel arrangement of a class AB transconductor having a transconductance and the source-drain path of a MOS transistor emulating a MOS resistor. The current output of the parallel arrangement is integrated and supplied as a control voltage to the gate electrode of the MOS transistor. By loop action the control voltage is adjusted and supplied to the floating MOS resistors.

Abstract: A comparator is provided that compares one or more input signals in a regenerative circuit. One or more switched isolate the signal inputs after regeneration has started but before regeneration has reached such an extent that large voltage swings in the regeneration circuit are transmitted back to the signal source and corrupt the signal source or neighboring circuits. Furthermore, as controlled by a control circuit, the instant of isolating the signal source can be dependent on the degree of regeneration such as being dependent on a predetermined degree of regeneration. The comparator may be incorporated in an electronic device such as an analog-to-digital converter or a wireless receiver or transceiver.

Abstract: An current mode analogue-to-digital converter uses a conversion stage which operates using a two-phase clock and which requires the input signal to be present during only one of the phases. A sample-and-hold circuit (120, 130, 135) samples the input signal during the first clock phase and during the second clock phase a quantised bit value is generated from a mirror of the held input current by a kickback-free comparator circuit (140). Also during the second clock phase a residue is generated using the quantised value and a non-mirrored version of the held input current. Optionally, two comparator circuits (140, 140?) may be used to provide two-level quantisation, enabling errors introduced by the current mirror to be corrected by a Redundant Signed Digit algorithm. Two pipelines of conversion stages (Si?, Si?) can be multiplexed to double the conversion rate.

Abstract: A balanced transconductor having a pair of voltage inputs and a pair of current outputs comprises a pair of single-ended transconductors, one in each signal path and a cancellation network. The cancellation network cancels at the inputs to the single-ended transconductors a common mode voltage appearing at the voltage inputs so that no common mode output current results. The cancellation network may comprise four half-size single-ended transconductors drawing half the supply current of full-size single-ended transconductors.

Abstract: An integrated circuit (100) comprising an analogue circuit (30) and optionally a digital circuit (50) couples substrate noise present on the integrated circuit ground rail (114) onto a supply rail (116) of the analogue circuit. The voltage difference between the supply rail and ground is therefore substantially independent of the noise, thereby reducing or eliminating the impact of the noise on signals in the analogue circuit.

Abstract: A balanced transconductor having a pair of voltage inputs and a pair of current outputs comprises a pair of single-ended transconductors, one in each signal path and a cancellation network. The cancellation network cancels at the inputs to the single-ended transconductors a common mode voltage appearing at the voltage inputs so that no common mode output current results. The cancellation network may comprise four half-size single-ended transconductors drawing half the supply current of full-size single-ended transconductors.

Abstract: An integrated circuit (100) comprising an analogue circuit (30) and optionally a digital circuit (50) couples substrate noise present on the integrated circuit ground rail (114) onto a supply rail (116) of the analogue circuit. The voltage difference between the supply rail and ground is therefore substantially independent of the noise, thereby reducing or eliminating the impact of the noise on signals in the analogue circuit.

Abstract: In order to enable non-integer current ratios to be produced in current mirror circuits using small transistors the channel area is adjusted by changes in the channel length over part of the width of the channel. In further embodiments the transistor is formed as two or more sub-transistors, the channel length of one sub-transistor being unequal to that of the other(s).

Abstract: A current mode pipelined analogue to digital converter (ADC) has a plurality of serially connected conversion stages. Each conversion stage has an input (40) for receiving a sampled and held current which is connected via a switch (S41) to a first current memory (M42) and via a switch (S40) to a second current memory (M41). The output of the second current memory (M41) is fed via a switch (S44) to one input of a summing junction (46). The output of the first current memory (M42) is fed via a switch (S42) to the input of a comparator (L44) whose output is clocked into a latch (L44) whose Q output is connected to an output (45) as the digital result of the conversion. The Q output of the latch (L44) is also connected to a digital to analogue converter (46) whose analogue output is fed to a second input of the summing junction 46 via a switch (S43) to form the analogue residue signal for application via output (47) to the next conversion stage in the pipeline.

Abstract: A current comparator comprises first (1) and second (2) inputs for receiving input currents to be compared. During a first phase (1a) of a clock period the input currents are sensed and stored on first (N1,S7) and second (N2,S8) current memory circuits. On a second phase (1b) of the clock period a switching arrangement (S1 to S4) inverts the input currents and applies them together with the currents stored in the first (N1,S7) and second (N2,S8) current memory circuits to a regenerative latch circuit (P1,P2,S9,S10). During a third phase (2a) of the clock period the comparator produces the comparison result at an output (3). During a fourth phase switches (S5,S6,S9,S10,S11) are operated to reset the comparator to its initial state.

Abstract: A switched current memory circuit has an input to which an input current (i) is applied and which is connected via a switch (S1) to the drain electrode of a memory transistor (M). A second switch (S3) is connected between the memory circuit input and the source electrode of a grounded gate transistor (G) whose drain electrode is connected to the gate electrode of the memory transistor (M). The drain electrode of the memory transistor (M) is connected via switch (S2) to an output at which an output current (i.sub.o) is produced.The second switch (S3) provides zero-voltage switching which reduces the effects of charge injection on the current stored.

Abstract: A current memory cell comprises a fine MOS memory transistor (T1) and a coarse MOS memory transistor (T2) connected in series between two power supply rails. Such current memory cells are preferably designed so that the sum of the voltage drops across the coarse and fine memory transistors when diode connected is equal to the supply voltage. In order to achieve this while leaving flexibility in choosing the transistor saturation voltages an auxiliary power rail (V.sub.dda) is generated using as a reference the voltage drops across two diode connected transistors (T6, T7) which conduct a current equal to the bias current in the current memory cell (3).

Abstract: A current memory for sampled analogue currents comprises a first, coarse, current memory cell and a second, fine, current memory cell. The first current memory cell senses the input current during a first portion of the first period of the clock cycle, while the second current memory cell senses the input current plus the current produced by the first current memory cell during a second portion of the first period of the clock cycle. The combined outputs of the first and second current memory cells is available during a second period of the clock cycle. The first current memory further comprises a voltage amplifier which increases the effective g.sub.m of a memory transistor in the first memory cell and holds the potential at the junction of the drain electrodes of the memory transistors in each of the memory cells close to a virtual earth.

Abstract: Circuit blocks for integrating/differentiating input signals in the form of sampled currents include coupled current memories where the second current memory has a plurality of scaled outputs which feed switching arrangements. Resistors are provided in the current memories, the resistance of the resistors being equal to the "on" resistance of the switching arrangement multiplied by any multiplying factor applied to this output to which the switching arrangement is coupled.

Abstract: A current memory comprises an input which is connected via a switch which is closed on a phase .phi.1 of a clock signal to inputs of a coarse memory cell (M1) and a fine memory cell(M2). The coarse memory cell samples the input current on phase .phi.1a of the clock and outputs a current thereafter. The fine memory cell senses the difference between the input current and the output of the coarse memory on phase .phi.1b of the clock. A second switch which is closed on phase .phi.2 of the clock passes the combined outputs of the coarse and fine memories to an output. Two further switches are provided which are closed for a short time (sh1) at the start of phase .phi.1b. The two further switches discharge the stray capacitance (C.sub.n) at the node (2) to the voltage reference source via a terminal.

Abstract: A current memory has an input (1) which is connected via a switch (S1) to inputs of a coarse memory cell (CM) and a fine memory cell (FM). On a phase .phi.1 of a clock signal the switch (S1) closes. During a first part .phi.1a of the clock .phi.1 of the coarse memory cell samples the input current and the outputs the sampled current thereafter. During a second part .phi.1b of the clock .phi.1 the fine memory cells senses and stores the difference between the input current and the output current of the coarse memory (CM). An output switch (S5) closes on phase .phi.2 of the clock, thereby passing the combined outputs of the coarse and fine memories to an output (2). A resistor r.sub.s is provided between the common nodes of the coarse and fine memories, having a resistance equal to the "on" resistance of the output switch (S5).

Abstract: A switched current differentiator includes first and second interconnected current memory cells, An input current is applied to terminal (1) and is fed on line (2) to the current memory cells, A first output current is derived from the first current memory cell via a transistor and a second output current is derived from the second current memory cell via another transistor. The second output current is inverted (A1) and summed with the first output current. The summed current is inverted (A2) and fed to an output via a switch on odd phases of a clock signal and is fed directly to the output via a further switch (S4) on even phases of a clock signal. A damped differentiator may be formed using a feeback loop. In a fully differential version of the differentiator the inverters may be constructed by the correct interconnection of the differential signals, i.e. by crossing over connections.

Abstract: A current memory for balanced current inputs comprises two coarse and two fine current memory cells each of which comprises a field effect transistor having a switch between its gate and source electrodes. Parasitic gate-drain capacitances are neutralised by capacitors connected between the gate and drain electrodes of opposite pairs of transistors. Other current transport errors can be compensated by providing appropriately dimensioned extra capacitance added to each of the neutralising capacitors.

Abstract: A switched current bilinear integrator comprising interconnected current memory cells (M1, M2) in which, during a first phase of a clock cycle, an input current is fed to the inputs of the current memory cells and during a second phase of the clock cycle an inverted version (A1) of the input current is fed to the inputs of the current memory cells. The output of the integrator is obtained by combining the output (optionally scaled) of the first current memory cell (M1) with an inverted (A2) version of the output (optionally scaled) of the second memory cell (M2). A lossy integrator may be formed by feeding back to the input a scaled version of the current stored in the second current memory cell and an inverted, scaled version of the current stored in the first memoy cell.