Abstract: Surface acoustic wave (SAW) identification tag discrimination methods including, in one embodiment (1) detecting a signal emanating from an electronic device operating within a SAW tag frequency band; (2) identifying a null period in a transmission pattern in the signal; and (3) effecting communication of information during the null period.

Abstract: A transfer function system for determining an identifier on a surface acoustic wave (SAW) identification tag and a method of operating the same. In one embodiment the system provides for (1) generating a radio frequency (RF) interrogation signal that causes a transducer located on a piezoelectric substrate to produce an initial acoustic pulse that reflects off of a plurality of reflectors arranged according to time and phase position on the substrate to yield response acoustic pulses, the transducer generating an RF response signal from the response acoustic pulses; and (2) determining the identifier by decoding the RF response signal in view of predefined time, phase and amplitude parameters.

Abstract: A method of accommodating code collisions from multiple SAW identification tag coded response pulses. In one embodiment, the method includes: (1) separating probable candidates by time-domain; (2) classifying the probable candidates by code-division separation; (3) employing known coded identification signals to adjust the probable candidates; and (4) correlating the multiple SAW identification tag coded response pulses to identify the probable candidates for further processing.

Abstract: A transfer function system for determining an identifier on a surface acoustic wave (SAW) identification tag and a method of operating the same. In one embodiment the system provides for (1) generating a radio frequency (RF) interrogation signal that causes a transducer located on a piezoelectric substrate to produce an initial acoustic pulse that reflects off of a plurality of reflectors arranged according to time and phase position on the substrate to yield response acoustic pulses, the transducer generating an RF response signal from the response acoustic pulses; and (2) determining the identifier by decoding the RF response signal in view of predefined time, phase and amplitude parameters.

Abstract: The present invention relates to the general matter of integration of Internet services and telephony services with a video display (e.g., a television set). In a preferred embodiment, the invention utilizes a personal computer for system intelligence with a connection from a set top box to receive enhanced feature requests originating from a user remote control device. The personal computer processes the requests and generates pop-up windows which are sent back to the set top box for insertion into the video image as interactive displays simultaneously with the entertainment content already found in the video image.

Abstract: The present invention relates to the general matter of integration of Internet services and telephony services with a video display (e.g., a television set). In a preferred embodiment, the invention utilizes a personal computer for system intelligence with a connection from a set top box to receive enhanced feature requests originating from a user remote control device. The personal computer processes the requests and generates pop-up windows which are sent back to the set top box for insertion into the video image as interactive displays simultaneously with the entertainment content already found in the video image.

Abstract: A digital desynchronizer (10) includes an elastic store unit (12) that receives a synchronously mapped asynchronous data signal (14) and outputs asynchronous output data over an asynchronous output data signal (20) in response to an output clock signal (22). The output clock signal (22) is generated by a digitally controlled oscillator (24). The digitally controlled oscillator (24) receives a speed up signal (28) and a slow down signal (30) from a jitter accumulator (26) in order to adjust the clock rate of the output clock signal (22). The jitter accumulator (26) compares retimed read address information (32) to write address information (34) from the elastic store unit (12), subtracts an initial bias, adds the result to any previous sum, and compares this final result to programmable threshold levels in order to determine whether or not to assert the speed up signal (28) or the slow down signal (30).

Abstract: A desynchronizer (10) for eliminating output mapping jitter includes a demapper circuit (12) for reading asynchronous data and a clock rate of an embedded signal within a synchronous channel (14). Payload data from the embedded signal is buffered within an elastic store circuit (17). The demapper circuit (12) outputs bit stuff and pointer justification timing adjustments to an overhead gapfill circuit (19) and a pointer justification leaky accumulator circuit (20). The overhead gapfill circuit (19) calculates overhead gaps within the payload data in order to generate a gapfill value (34). The pointer justification leaky accumulator circuit (20) determines the bit stuffs and pointer justifications occurring in the payload data in order to produce an accumulated value (36).

Abstract: An integrated office controller (IOC) network includes, in combination, a plurality of station devices each capable of transmitting and receiving multiplexed bearer and signal channel information; user port interface means for carrying said multiplexed information between a station device and a station multiplex/demultiplex device (SMX); a plurality of SMXs, each associated with and coupled to a predefined cluster of said station devices, via said user port interface means, for concentrating the multiplexed information froms said interface means into channel signals, central equipment module (CEM) means, including a call processor, a non-blocking switch matrix and clock means, for switching channel signals through said switch matrix under the control of said cell processor and clock means; transmission system means, capable of interfacing SMXs and trunk cards to said CEM, where said transmission system means includes modular line interface module (LIM) means for interfacing a plurality of SMXs and the CEM, an

Abstract: Programmable feature card circuitry includes: a signal processor with parallel input/output (I/O) data ports and responsive to command of the PBX call processor, signal memory, and a signal interface for converting the PBX signal format to a processor compatible format; the signal memory including program memory for storing signal processor program signals representing the programmed algorithm to be performed by the signal processor in the execution of the user selected PBX support function and including data memory for storing data signals from the PBX, the signal processor executing the stored programmed algorithm in response to the command signals from the PBX call processor.

Abstract: An integrated digital network (IDN) includes a matrix and user signal ports for exchanging voice, data, IDN control, and building control digital signals between the matrix and user equipment, the digital signals comprising single samples of each signal type from each user port in each IDN sample time interval, the IDN further including a transmission system for concentrating user port digital signal samples of each sample time interval, by common signal type, into multiple bit channel signals for exchange between the user ports and matrix signal ports of the matrix switch, the matrix switch interconnecting each channel signal from one or more user ports to one or more other user ports.

Abstract: A simple system is disclosed for detecting an 8 PSK (Phase Shift Keyed) - PRS (Partial Response System) signal output set, and other multi-level PSK and APSK (Amplitude and Phase Shift Keyed) - PRS signal sets. Quadrature interdependent channel decision feedback translates a reduced output signal set which is a scaled down version of the original full response input signal set before partial response filtering. The reduced output signal set has the same number of points and the same distribution array pattern as the input signal set. This enables the use of a conventional detector which need only detect the reduced signal set, not the complete output signal set. A decoder controls selection of predetermined interdependent signal value adjustments for each channel to translate the reduced output signal set in accordance with each successive signal relative to the then current signal value.

Abstract: A high density bandlimited digital transmission system with a transmitter and a receiver connected by a radio path with an end-to-end channel transfer function selected to form at the receiver either raised cosine pulses or partial response pulses. The transmitter is partitioned or divided into an active pulse forming network and a passive pulse shaping and bandlimiting network. The active and passive networks are concatenated and in combination provide an optimal transmitter-receiver combination for raised cosine or for partial response signaling. Transmit and receive filters provide optimal signal pulse shaping while meeting specified out-of-band signal suppression.In-phase and quadrature phase carriers (I and Q channels) work with rectangular or half-wave sinusoidal modulating pulses. Further, time-offset or time-coincident pulses on each of the respective I and Q channels are used. Multi-level embodiments are also disclosed.

Abstract: A marker circuit communicating with a stored program controller and switch stages, implementing pathfinding, connect, and disconnect operations while using address, status, and data buses to control the switch through exchange of connect information from the stored program controller and disconnect information from the switch control stores.

Abstract: A time folded time space time (TST) switch with the establishing of a communication through path in one direction automatically establishing a path in the opposite direction in an adjacent time slot. With one transfer through a space switch made during an even time slot, the other transfer is made in a symmetrical fashion during the following odd time slot. This time folded TST switch selectively interconnects digital bi-directional Time Division Multiplexed (TDM) transmission paths.

Abstract: A time space time (TST) switch using two basic modules, a time switching module and a space switching module with individual module elements interconnectable to realize a great range of time division switch sizes and configurations. Control stores and state stores associated with respective switching elements are combined and incorporated into the time switch and space switch modules.