Patents by Inventor John E. Watkins

John E. Watkins has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100306416
    Abstract: A system includes a virtualized I/O device coupled to one or more processing units. The virtualized I/O device includes programmed I/O (PIO) configuration registers corresponding to hardware resources, and a storage for storing a resource table that includes a plurality of entries. Each entry corresponds to a respective hardware resource. A system processor may allocate the hardware resources to functions that may include physical and virtual functions, and may program each entry of the resource discovery table for each function with an encoded value that indicates whether a requested hardware resource has been allocated to a requesting process, and whether the requested hardware resource is shared with another function. Processing units may execute a device driver instance associated with a given process to discover allocated resources by requesting access to the resource discovery table. The virtualized I/O device protects the resources by checking access requests against the resource discovery table.
    Type: Application
    Filed: May 26, 2009
    Publication date: December 2, 2010
    Inventor: John E. Watkins
  • Patent number: 7836328
    Abstract: A method and apparatus for recovering from errors occurring during system bus transactions. An input/output device such as a network interface unit (NIU) issues read and write operations across a meta interface coupling the device to host bus (glue) logic. The host bus logic translates the operations into system bus transactions. The device maintains a set of reusable identifiers for identifying the operations, and a table maintained by the device or the host bus logic maps the operation identifiers to transaction identifiers identifying the system bus transactions spawned to perform the operations. If a bus transaction encounters an unrecoverable error, the host bus logic reports the error to the device and drops any further data received from other bus transactions performed for the same operation. The device marks the operation's identifier as dirty, to prevent its reuse. The operation identifier may be reused after software clears the error condition.
    Type: Grant
    Filed: May 4, 2006
    Date of Patent: November 16, 2010
    Assignee: Oracle America, Inc.
    Inventors: Rahoul Puri, John E. Watkins, Arvind Srinivsan, Babu R. Kandimalla, Nimita Taneja
  • Publication number: 20100185782
    Abstract: A method for reducing address space in a shared virtualized I/O device includes allocating hardware resources including variable resources and permanent resources, to one or more functions. The method also includes allocating address space for an I/O mapping of the resources in a system memory, and assigning a respective portion of that address space for each function. The method further includes assigning space within each respective portion for variable resources available for allocation to the function to which the respective portion is assigned, and further assigning space within each respective portion for a set of permanent resources that have been allocated to the function to which the respective portion is assigned. The method further includes providing a translation table having a plurality of entries, and storing within each entry of the translation table, a different internal address of a permanent resource that has been allocated to a particular function.
    Type: Application
    Filed: January 19, 2009
    Publication date: July 22, 2010
    Inventor: John E. Watkins
  • Publication number: 20100100717
    Abstract: An I/O device having function level reset functionality includes a host interface that may include a master reset unit, a plurality of client interfaces, each corresponding to one or more functions, and a plurality of hardware resources. Each hardware resource may be associated with a respective function. In response to receiving a reset request to reset a specific function, the master reset unit may provide to each client interface, a request signal corresponding to the reset request, and a signal identifying the specific function. Each client interface having an association with the specific function may initiate a reset operation of the associated hardware resources, and also provide a client reset done signal for the specific function to the master reset unit in response to completion of the reset operations of the hardware resources. The master reset unit provides a reset done signal for the specific function to the host interface.
    Type: Application
    Filed: October 22, 2008
    Publication date: April 22, 2010
    Inventors: Rahoul Puri, Arvind Srinivasan, Louise Y. Yeung, Marcelino M. Dignum, John E. Watkins
  • Publication number: 20090307702
    Abstract: A system includes a virtualized I/O device coupled to one or more processing units. The virtualized I/O device includes a storage for storing a resource discovery table, and programmed I/O (PIO) configuration registers corresponding to hardware resources. A system processor may allocate the plurality of hardware resources to one or more functions, and to populate each entry of the resource discovery table for each function. The processing units may execute one or more processes. Given processing units may further execute OS instructions to allocate space for an I/O mapping of a PIO configuration space in a system memory, and to assign a function to a respective process. Processing units may execute a device driver instance associated with a given process to discover allocated resources by requesting access to the resource discovery table. The virtualized I/O device protects the resources by checking access requests against the resource discovery table.
    Type: Application
    Filed: June 9, 2008
    Publication date: December 10, 2009
    Inventor: John E. Watkins
  • Publication number: 20090015397
    Abstract: An emergency communication device is disclosed herein, including a substantially enclosed housing, at least one receiver, at least one transformer, at least one latching relay, at least one power supply, wherein the receiver, transformer, latching relay, and power supply are located within the housing, a telephone cord, an automatic dialer, wherein the automatic dialer is operatively connected to the housing, and is operatively connected to at least the power supply, and a flashing light.
    Type: Application
    Filed: July 10, 2008
    Publication date: January 15, 2009
    Applicant: ALLERT ALL, INC.
    Inventors: DAVID J. EARDLEY, NORBERT J. TOBBE, JOHN E. WATKINS
  • Patent number: 7124319
    Abstract: A fault tolerant computing system is provided comprising two or more processing sets that operate in synchronism with one another. The two processing sets are joined by a bridge, and there is a communications link for each processing set for transmitting data from the processing set to the bridge. Data transmissions are initiated in synchronism with one another from the respective processing sets to the bridge but are then subject to variable delay over the communications link. Accordingly, a buffer is included in the bridge for storing the data transmissions received from the processing sets for long enough to compensate for the variable delay. The data transmissions can then be fed out from the buffer to a comparator that verifies that the data transmissions received from the two or more processing sets properly match each other. Likewise, a buffer is included in each processing set for storing the data transmissions received from the bridge for long enough to compensate for the variable delay.
    Type: Grant
    Filed: March 14, 2003
    Date of Patent: October 17, 2006
    Assignee: Sun Microsystems, Inc.
    Inventors: John E. Watkins, Paul J. Garnett, Stephen Rowlinson
  • Patent number: 7099984
    Abstract: A computing system comprises two or more processing sets, for example for fault tolerant operation. The multiple processing sets have a connection to at least one device, typically many devices. The ownership of each device is allocated to one of the two or more processing sets. When an interrupt is generated within a device, this is transmitted from the device to the processing set to which ownership of the device has been allocated, but not to the remaining processing sets. In addition, a command for a device may be generated by a processing set. However, receipt of this command by the device is disabled if the processing set that generated the command has not been allocated ownership of the device.
    Type: Grant
    Filed: March 14, 2003
    Date of Patent: August 29, 2006
    Assignee: Sun Microsystems, Inc.
    Inventors: John E. Watkins, Paul J. Garnett, Stephen Rowlinson
  • Publication number: 20030182492
    Abstract: A computing system comprises two or more processing sets, for example for fault tolerant operation. The multiple processing sets have a connection to at least one device, typically many devices. The ownership of each device is allocated to one of the two or more processing sets. When an interrupt is generated within a device, this is transmitted from the device to the processing set to which ownership of the device has been allocated, but not to the remaining processing sets. In addition, a command for a device may be generated by a processing set. However, receipt of this command by the device is disabled if the processing set that generated the command has not been allocated ownership of the device.
    Type: Application
    Filed: March 14, 2003
    Publication date: September 25, 2003
    Applicant: Sun Microsystems, Inc.
    Inventors: John E. Watkins, Paul J. Garnett, Stephen Rowlinson
  • Publication number: 20030182594
    Abstract: A fault tolerant computing system is provided comprising two or more processing sets that operate in synchronism with one another. The two processing sets are joined by a bridge, and there is a communications link for each processing set for transmitting data from the processing set to the bridge. Data transmissions are initiated in synchronism with one another from the respective processing sets to the bridge but are then subject to variable delay over the communications link. Accordingly, a buffer is included in the bridge for storing the data transmissions received from the processing sets for long enough to compensate for the variable delay. The data transmissions can then be fed out from the buffer to a comparator that verifies that the data transmissions received from the two or more processing sets properly match each other. Likewise, a buffer is included in each processing set for storing the data transmissions received from the bridge for long enough to compensate for the variable delay.
    Type: Application
    Filed: March 14, 2003
    Publication date: September 25, 2003
    Applicant: Sun Microsystems, Inc.
    Inventors: John E. Watkins, Paul J. Garnett, Stephen Rowlinson
  • Patent number: 6480489
    Abstract: A system and method are provided for transferring a packet received from a network to a host computer according to an operation code associated with the packet. A packet received at a network interface is parsed to retrieve information from a header portion of the packet. A flow key is generated for a received packet that was formatted with one of a set of predetermined protocols. A packet's flow key identifies a communication flow that comprises the packet. Based on some of the retrieved information, a code is associated with the packet to inform a transfer engine how the packet should be transferred to host memory. Based on a packet's code, the transfer engine stores the packet in one or more host memory buffers. If the packet was formatted with one of the set of predetermined protocols, its data is re-assembled in a re-assembly buffer with data from other packets in the same communication flow. Re-assembled data may be provided to a destination application or user through page flipping.
    Type: Grant
    Filed: March 1, 1999
    Date of Patent: November 12, 2002
    Assignee: Sun Microsystems, Inc.
    Inventors: Shimon Muller, Denton E. Gentry, Jr., Linda T. Cheng, John E. Watkins
  • Patent number: 6453360
    Abstract: A high performance network interface is provided for receiving a packet from a network and transferring it to a host computer system. A header portion of a received packet is parsed by a parser module to determine the packet's compatibility with, or conformance to, one or more pre-selected protocols. If compatible, a number of processing functions may be performed to increase the efficiency with which the packet is handled. In one function, a re-assembly engine re-assembles, in a re-assembly buffer, data portions of multiple packets in a single communication flow or connection. Header portions of such packets are stored in a header buffer. An incompatible packet may be stored in another buffer. In another function, a packet batching module determines when multiple packets in one flow are transferred to the host computer system, so that their header portions are processed collectively rather than being interspersed with headers of other flows' packets.
    Type: Grant
    Filed: March 1, 1999
    Date of Patent: September 17, 2002
    Assignee: Sun Microsystems, Inc.
    Inventors: Shimon Muller, Denton E. Gentry, Jr., John E. Watkins, Linda T. Cheng
  • Patent number: 6105110
    Abstract: A circuit used to control the modification of content within memory implemented within an address translation unit. This memory includes a plurality of entries which contain virtual and physical addresses associated with an address translation. The circuit includes an update control circuit coupled to the address translation circuit. The update circuit is configured to set an entry to an invalid state or point to an entry to be loaded with a new address translation. The circuit further includes a flush control circuit that is configured to control the update control circuit. Such control includes setting an entry to an invalid state upon detecting a particular event.
    Type: Grant
    Filed: November 8, 1999
    Date of Patent: August 15, 2000
    Assignee: Sun Microsystems, Inc.
    Inventor: John E. Watkins
  • Patent number: 6073224
    Abstract: A circuit and method for segregating address entries of memory, internal to an address translation unit, into locked and unlocked regions. The locked region is a portion of the memory that can be invalidated by a lesser number of events than the unlocked region. In one embodiment, replacement circuitry of the address translation unit may invalidate address translations only stored in the unlocked region. The replacement circuitry comprises a counter to produce a first count value upon detecting that at least a first command has been issued to the address translation unit and each entry of the memory is currently in a valid state. Also, the replacement circuitry comprises an increment controller to control the counter to produce the first count value that addresses an entry of the memory within the second address range.
    Type: Grant
    Filed: July 1, 1996
    Date of Patent: June 6, 2000
    Assignee: Sun Microsystems, Inc.
    Inventor: John E. Watkins
  • Patent number: 6049857
    Abstract: An apparatus and method for translating a virtual address to a physical address utilizing an address translation unit implemented within a network interface card is described. The address translation unit of the present invention is utilized in a computer system. The computer system comprises a first bus; processors with embedded caches and memory coupled to the first bus; a second bus; a network logic coupled to the second bus, wherein the network logic includes an address translation unit; and a bus bridge coupled to the first bus and to the second bus.
    Type: Grant
    Filed: July 23, 1998
    Date of Patent: April 11, 2000
    Assignee: Sun Microsystems, Inc.
    Inventor: John E. Watkins
  • Patent number: 5991854
    Abstract: A circuit used to control the modification of content within memory implemented within an address translation unit. This memory includes a plurality of entries which contain virtual and physical addresses associated with an address translation. The circuit includes an update control circuit coupled to the address translation circuit. The update circuit is configured to set an entry to an invalid state or point to an entry to be loaded with a new address translation. The circuit further includes a flush control circuit that is configured to control the update control circuit. Such control includes setting an entry to an invalid state upon detecting a particular event.
    Type: Grant
    Filed: July 1, 1996
    Date of Patent: November 23, 1999
    Assignee: Sun Microsystems, Inc.
    Inventor: John E. Watkins
  • Patent number: 5983332
    Abstract: An apparatus and method for translating a virtual address to a physical address utilizing an address translation unit implemented within a network interface card is described. The address translation unit of the present invention is utilized in a computer system. The computer system comprises a first bus; processors with embedded caches and memory coupled to the first bus; a second bus; a network logic coupled to the second bus, wherein the network logic includes an address translation unit; and a bus bridge coupled to the first bus and to the second bus.
    Type: Grant
    Filed: July 1, 1996
    Date of Patent: November 9, 1999
    Assignee: Sun MicroSystems, Inc.
    Inventor: John E. Watkins
  • Patent number: 5937436
    Abstract: A network interface circuit including an address translation unit and a flush check circuit, and a method for checking for an invalid address translation within of the address translation unit, are disclosed. A flush check circuit, in communication with the address translation unit, is implemented to determine, prior to loading an address translation into the internal memory, whether one of the plurality of entries already contains a virtual address utilized by the address translation. If so, an error has occurred with the flushing operations of the address translation unit because the address translation should have already been removed. In response, the flush check circuit signals logic to perform error handling techniques such as issuing an error signal, storing the invalid address translation unit, or transmitting the virtual address of the address translation without loading that address translation.
    Type: Grant
    Filed: July 1, 1996
    Date of Patent: August 10, 1999
    Assignee: Sun Microsystems, Inc
    Inventor: John E. Watkins
  • Patent number: 5871804
    Abstract: The invention disclosed relates to a composition and method for enhancing the contrast of the lipid component of fingerprints and the like. The composition includes a metal chelate of the structural formula I ##STR1## wherein R is a UV-absorbing aromatic group, X is an electron attracting group, G is a synergic group containing a suitable polar functional group, and M is a metal ion, a suitable water-soluble organic solvent and water, at pH of 3 to 10.
    Type: Grant
    Filed: June 23, 1995
    Date of Patent: February 16, 1999
    Assignee: Her Majesty the Queen in right of Canada as represented by the Solicitor General Acting Through the Commissioner of the Royal Canadian Mounted Police
    Inventors: Della A. Wilkinson, John E. Watkin
  • Patent number: 5854911
    Abstract: A prefetch apparatus optimizes bandwidth in a computer network by prefetch accessing data blocks prior to their demand in an ATM network thereby effectively reducing memory read latency. The method of the preferred embodiment includes the steps of: 1) computing a prefetch address of a next sequential data block given an address of a requested data block; 2) comparing a current request address against a previously computed prefetch address; and 3) generating a hit/miss indication corresponding to whether the current request address matches the previously computed prefetch address.
    Type: Grant
    Filed: July 1, 1996
    Date of Patent: December 29, 1998
    Assignee: Sun Microsystems, Inc.
    Inventor: John E. Watkins