Patents by Inventor John F. Zumkehr
John F. Zumkehr has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7729168Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for reduced signal level support for memory devices. In some embodiments, a host includes one or more additional electrical contacts to provide a controllable voltage reference to a memory device. The host may also include driver circuitry to provide a driver signal to the memory device. In some embodiments, the driver signal is substantially symmetrical around the controllable voltage reference.Type: GrantFiled: June 28, 2007Date of Patent: June 1, 2010Assignee: Intel CorporationInventors: John F. Zumkehr, James E. Chandler, Jeffrey E. Smith
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Patent number: 7623032Abstract: The object control and tracking system of the present invention includes a computer, a system controller, and at least one object storage drawer housed within a security cabinet. The system controller provides a bi-directional communication link between the computer and a printed circuit board located within the object storage drawer. The objects are symmetrically shaped acrylic key fobs each containing a touch memory device to store information about as set of keys or other valuable objects associated with the fob. A dress plate, incorporating a plurality of slots for interfacing with the fobs, is within the drawer and provides the mechanical support for the key fobs. The key fobs are generally symmetrically shaped to fit into the slot. The slot spacing is staggered in the array so that it is easier for a user to replace or to locate the key fob if the array is almost fully occupied.Type: GrantFiled: December 5, 2002Date of Patent: November 24, 2009Assignee: Key Control Holding, Inc.Inventors: Roger A. Niederland, John F. Zumkehr, James E. Chandler
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Publication number: 20090080266Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for a double data rate (DDR) low power idle mode through reference offset. In some embodiments, a host offsets a reference voltage from a termination voltage of a command/address interconnect when the interconnect is tri-stated. Other embodiments are described and claimed.Type: ApplicationFiled: September 25, 2007Publication date: March 26, 2009Inventor: John F. Zumkehr
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Publication number: 20090003112Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for reduced signal level support for memory devices. In some embodiments, a host includes one or more additional electrical contacts to provide a controllable voltage reference to a memory device. The host may also include driver circuitry to provide a driver signal to the memory device. In some embodiments, the driver signal is substantially symmetrical around the controllable voltage reference.Type: ApplicationFiled: June 28, 2007Publication date: January 1, 2009Inventors: JOHN F. ZUMKEHR, James E. Chandler, Jeffrey E. Smith
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Patent number: 7152008Abstract: In general, in one aspect, the disclosure describes an apparatus for calibrating signals. The apparatus includes a receiver pair to receive a differential signal and a reference signal and to generate at least one comparison signal reflecting where a first signal of the differential signal and a second signal of the differential signal cross each other with respect to the reference signal. The second signal is a negative compliment of the first signal. The apparatus further includes a phase detector to determine a phase error based on the at least one comparison signal. The apparatus also includes an edge delay control driver pair to adjust the differential signal based on the phase error.Type: GrantFiled: December 15, 2004Date of Patent: December 19, 2006Assignee: Intel CorporationInventors: John F. Zumkehr, James E. Chandler, Renjeng Chiang
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System and method for dynamic rank specific timing adjustments for double data rate (DDR) components
Patent number: 7127584Abstract: In some embodiments, a system and method for making rank-specific adjustments to the READ tenure parameters of a double data-rate (DDR) memory component to improve the DDR bus timing margins. When a READ tenure is encountered for the DDR memory component, the rank of the DDR memory component is calculated and the value is used to retrieve two adjustment signals, which are specific to the DDR memory component, from the look up table. One of the adjustment signals is used to adjust a gating signal for the data strobe signal of the component. The other adjustment signal is used to fine tune a required ΒΌ clock delay for the data strobe signal to read the data from the DDR memory component while adjusting for the inherent latency of the DDR memory component. Other embodiments are described and claimed.Type: GrantFiled: November 14, 2003Date of Patent: October 24, 2006Assignee: Intel CorporationInventors: Derek A. Thompson, Darrell S. McGinnis, John F. Zumkehr -
Patent number: 7095245Abstract: Embodiments of the invention include a memory controller to interface to memory. In one embodiment, the memory controller includes a pull-up calibration terminal to couple to an external pull-up resistor, a pull-down calibration terminal to couple to an external pull-down resistor, a voltage reference node, a first switch coupled between the pull-up calibration terminal and the voltage reference node, and a second switch coupled between the pull-down calibration terminal and the voltage reference node. The first switch and the second switch may be selectively closed to generate an internal voltage reference on the voltage reference node in a normal mode that may be used for comparison with an input signal to receive data.Type: GrantFiled: November 14, 2003Date of Patent: August 22, 2006Assignee: Intel CorporationInventors: John F. Zumkehr, James E. Chandler, Ray I. Chiang
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Patent number: 7071728Abstract: According to one embodiment of the present invention, a circuit is disclosed. The circuit includes a plurality of driver slices, a portion of the plurality of the driver slices being used to provide a target impedance; a digital matching logic to select the portion of the plurality of the driver slices; and an analog matching circuit to produce a bias voltage to match pull-up and pull-down.Type: GrantFiled: November 30, 2004Date of Patent: July 4, 2006Assignee: Intel CorporationInventors: James E. Chandler, John F. Zumkehr, Arnaud Forestier
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Patent number: 7046062Abstract: A device and method for calibrating a slew rate is disclosed. The slew rate may be for a driver of a bi-directional buffer. A driver outputs a signal having a frequency. A receiver is coupled to the driver. A frequency counter measures the frequency of the signal. A calibrated slew rate is determined by the frequency of a waveform of the signal. Different waveforms may be determined for the pull-up and pull-down calibrations.Type: GrantFiled: March 8, 2005Date of Patent: May 16, 2006Assignee: Intel CorporationInventors: John F. Zumkehr, James E. Chandler
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Patent number: 7036053Abstract: A method for optimizing a source synchronous clock reference signal timing to capture data from a memory device (e.g., DDR SDRAM) includes conducting an iterative two-dimensional data eye search for optimizing the delay of the source synchronous clock reference signal (e.g., DQS). Embodiments of the present invention are directed to tuning the delay for each device for the optimal margin in two dimensions: maximize the distance from the data eye walls and maximize the noise margin on the interface. An iterative data eye search is performed while varying the DQS delay timing and noise margin.Type: GrantFiled: December 19, 2002Date of Patent: April 25, 2006Assignee: Intel CorporationInventors: John F. Zumkehr, John L. Bryan, Howard S. David, Klaus Ruff
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Patent number: 6965529Abstract: Methods, apparatus and machine-readable medium to terminate a memory bus line. In some embodiments, the memory bus line is terminated with one or more transistors of an output buffer that are used to drive the memory bus line during a memory write.Type: GrantFiled: June 21, 2002Date of Patent: November 15, 2005Assignee: Intel CoprorationInventors: John F. Zumkehr, James E. Chandler
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Patent number: 6922077Abstract: According to one embodiment of the present invention, a circuit is disclosed. The circuit includes a plurality of driver slices, a portion of the plurality of the devices being used to provide a target impedance; a digital matching logic to select the portion of the plurality of the driver slices; and an analog matching circuit to produce a bias voltage to match pull-up and pull-down.Type: GrantFiled: June 27, 2003Date of Patent: July 26, 2005Assignee: Intel CorporationInventors: James E. Chandler, John F. Zumkehr, Arnaud Forestier
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Patent number: 6918048Abstract: A system, method and medium may delay a strobe signal based upon a delay base and a delay adjustment to reduce effects of process variations and/or environmental changes.Type: GrantFiled: September 6, 2001Date of Patent: July 12, 2005Assignee: Intel CorporationInventor: John F. Zumkehr
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Patent number: 6901494Abstract: According to one aspect of the invention, a method is provided in which one or more write commands and their corresponding write data are received from a first device. The corresponding write data may be delayed by the first device by a first delay period. The one or more write commands and their corresponding write data are stored in a set of buffers. In response to another write command being received from the first device, a buffered write command and its corresponding write data are sent to a second device for execution, without waiting for the write data corresponding to said another write command to be sent from the first device.Type: GrantFiled: July 14, 2003Date of Patent: May 31, 2005Assignee: Intel CorporationInventors: John F. Zumkehr, Pete D. Vogt
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Patent number: 6864731Abstract: A device and method for calibrating a slew rate is disclosed. The slew rate may be for a driver of a bi-directional buffer. A driver outputs a signal having a frequency. A receiver is coupled to the driver. A frequency counter measures the frequency of the signal. A calibrated slew rate is determined by the frequency of a waveform of the signal. Different waveforms may be determined for the pull-up and pull-down calibrations.Type: GrantFiled: May 19, 2003Date of Patent: March 8, 2005Assignee: Intel CorporationInventors: John F. Zumkehr, James E. Chandler
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Publication number: 20040263204Abstract: According to one embodiment of the present invention, a circuit is disclosed. The circuit includes a plurality of driver slices, a portion of the plurality of the driver slices being used to provide a target impedance; a digital matching logic to select the portion of the plurality of the driver slices; and an analog matching circuit to produce a bias voltage to match pull-up and pull-down.Type: ApplicationFiled: June 27, 2003Publication date: December 30, 2004Inventors: James E. Chandler, John F. Zumkehr, Arnaud Forestier
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Patent number: 6785842Abstract: Systems and methods for transient error recovery in pipelined reduced instruction set computer (RISC) processors prevent state changes based on the execution of an instruction until the execution of the instruction is validated. If a transient fault occurs causing an error to appear in an instruction execution, the instruction is retrieved using an instruction fetch address associated with that instruction and is stored in a pipeline history cache. The RISC processor pipeline is then restarted with that instruction. The validation of the execution of an instruction may take place in the execution stage, though processors with high clock frequencies may include a separate validate stage in the pipeline so that there is adequate time to validate the execution of the instruction without having to decrease the clock frequency.Type: GrantFiled: March 13, 2001Date of Patent: August 31, 2004Assignees: McDonnell Douglas Corporation, TRW, Inc.Inventors: John F. Zumkehr, Amir A. Abouelnaga
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Publication number: 20040123207Abstract: A method for optimizing a source synchronous clock reference signal timing to capture data from a memory device (e.g., DDR SDRAM) includes conducting an iterative two-dimensional data eye search for optimizing the delay of the source synchronous clock reference signal (e.g., DQS). Embodiments of the present invention are directed to tuning the delay for each device for the optimal margin in two dimensions: maximize the distance from the data eye walls and maximize the noise margin on the interface. An iterative data eye search is performed while varying the DQS delay timing and noise margin.Type: ApplicationFiled: December 19, 2002Publication date: June 24, 2004Applicant: Intel CorporationInventors: John F. Zumkehr, John L. Bryan, Howard S. David, Klaus Ruff
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Publication number: 20040111323Abstract: The object control and tracking system of the present invention includes a computer, a system controller, and at least one object storage drawer housed within a security cabinet. The system controller provides a bi-directional communication link between the computer and a printed circuit board located within the object storage drawer. The objects are symmetrically shaped acrylic key fobs each containing a touch memory device to store information about as set of keys or other valuable objects associated with the fob. A dress plate, incorporating a plurality of slots for interfacing with the fobs, is within the drawer and provides the mechanical support for the key fobs. The key fobs are generally symmetrically shaped to fit into the slot. The slot spacing is staggered in the array so that it is easier for a user to replace or to locate the key fob if the array is almost fully occupied.Type: ApplicationFiled: December 5, 2002Publication date: June 10, 2004Inventors: Roger A. Niederland, John F. Zumkehr, James E. Chandler
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Publication number: 20040093388Abstract: Embodiments of a method and/or an apparatus to test a delay lock loop circuit, chipset, or memory controller or memory controller hub (MCH) are described.Type: ApplicationFiled: November 13, 2002Publication date: May 13, 2004Inventors: James E. Chandler, John F. Zumkehr