Abstract: A phase lock loop comprises a voltage controlled oscillator, a phase detector and a loop filter comprising a charge pump and a filter network. The voltage controlled oscillator generates an output signal having a frequency which is responsive to a control voltage. The phase detector is responsive to the output signal and to a reference signal to generate a control signal indicative of a phase difference of the output signal and the reference signal. The charge pump is responsive to the control signal and to the control voltage to apply a charge indicative of both the phase difference and the control voltage to the filter network to develop the control voltage. Because the charge supplied by the charge pump depends on the control voltage as well as the phase difference of the output signal and the reference signal, the rate of adjustment of the output signal frequency depends on the present output signal frequency.

Abstract: In a method for making integrated circuits, a semiconductor substrate is provided which carries a plurality of unconnected devices of a first device type at regularly spaced regions of the substrate and a plurality of unconnected devices of a secound, distinct device type at substantially all regions of the substrate other than those carrying devices of the first device type, and at least one interconnection layer is formed on the substrate to interconnect selected ones of the devices of the first device type and the devices of the second device type to define a plurality of integrated circuits. Pad regions may be formed over unconnected devices for connection of the integrated circuits to package terminals. The integrated circuits are separated by regions containing unconnected devices, and the semiconductor substrate may be scribed and broken or otherwise cut in these regions to separate the integrated circuits.

Abstract: In a double polysilicon integrated circuit processing method a first level polysilicon is used for FET gate fabrication, a second level is used for interconnection and both levels are used in the fabrication of analog capacitors over field oxide regions. By the invention, capacitors are also fabricated in the FET device well by implanting dopant through the second level polysilicon at the same time that dopant is implanted directly into other regions of the substrate to a greater depth and dopant level concentration so as to function as an FET source. The method is particularly adapted to fabricating DRAM memories.

Abstract: A stream of high-speed bipolar signals transmitted along standard twisted pair telephone wiring are detected by a circuit that includes a pair of differential amplifiers each having a signal input connected directly to one conductor of the twisted pair and a reference input connected through a peak voltage detector to the opposite conductor. The amplifiers function as an input signal comparator which generates a corresponding bit stream of logical ones in response to the bipolar signals that exceed 50% of the average peak voltage input. A threshold bias voltage corresponding to positive going signals on each conductor is generated by the detector and charges separate capacitors that connect each reference input to its conductor. The bias voltage and bipolar signals input to each amplifier are algebraically summed which doubles the differential input signal and results in an increased signal to noise ratio of about six decibels.

Abstract: High-speed bipolar signals transmitted along standard twisted pair telephone wiring are subject to InterSymbol Interference which is corrected by an equalizer circuit that is operably responsive to predetermined parameters of bipolar signals detected at the secondary of a line transformer. These parameters are input to a control logic circuit which includes several stages, each producing a set of past dependent logical control signals which are input to corresponding equalizer tap circuits having outputs connected to a common output bus. Each tap circuit includes an integrator that is incrementally charged and discharged by an electronically switched capacitor. A tap weight voltage output from each integrator is subsequently summed directly or inversely by a second switched capacitor under control of the logical input signals.

Abstract: A variable oscillator, suitable for integration as part of a phase lock loop (PLL) clock source in a complementary metal oxide semiconductor (CMOS) integrated circuit, includes an amplifier and terminals for connection to a tank circuit, for example a crystal resonator. Capacitors are alternately coupled and decoupled in relation to the amplifier to cause oscillatory operation at lower and higher frequencies. In the CMOS circuit the reactance is conveniently provided by conductive layers of predetermined dimensions being carried by an oxide layer. Each layer provides a capacitive reactance which is arranged in series with a field effect device being controlled by associated PLL control circuitry. The control circuit includes a strobe generator for strobing a phase detector in response to a data signal received by an associated receiver. Each time the phase detector is strobed it registers one of an early or late phase indication. The phase indication is used to control the field effect devices.

Abstract: One of two capacitors in a phase comparator is discharged for a logic zero data input and is alternately charged with opposite polarities, depending on the state of a regenerated clock signal, for a logic one data input. The resultant charge of the capacitor when the data input again becomes zero is used to control a variable frequency oscillator which produces the clock signal, while the other of the two capacitors is discharged and then charged in the same manner. A phase locked loop including the phase comparator can accommodate arbitrary data sequences of a return-to-zero data signal and does not require a low pass filter.

Abstract: An oscillator including an amplifier which is formed by CMOS inverters and has a positive feedback path from an output to an input of the amplifier. The positive feedback path includes a capacitor which is alternately charged and discharged by switched constant current devices controlled by the amplifier and connected to the amplifier input. The amplifier includes a second capacitor in a negative feedback path to limit voltage swings at the amplifier input. The constant charging and discharging currents can be produced by current mirrors which are controlled to control the oscillation frequency.

Abstract: The subject invention is a sample-and-hold circuit that provides current gain and that is suitable for construction according to LSI (large scale integration) techniques. The circuit incorporates a bipolar transistor biased on (in the "sample" mode) to a predetermined quiescent state. A capacitor is connected across the output of the circuit (i.e. across the output of the bipolar transistor) to be charged to a certain voltage by the bipolar transistor and to store this voltage when the sample-and-hold circuit is in the "hold" mode of operation. IGFETs (insulated gate field effect transistors) are employed to bias the bipolar transistor and to switch the circuit from one mode of operation to the other.