Patents by Inventor John G. McDonough

John G. McDonough has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20040247019
    Abstract: This disclosure is generally directed to communication systems, devices used in communication systems and associated methods which may implement parallel hypothesis search techniques. The disclosed parallel hypothesis search techniques may permit a hypothesis to be dismissed early (i.e., before hypotheses in other searchers have completed their evaluation). Early hypothesis dismissal permits a new hypothesis to be loaded into the searcher while other searchers advantageously continue to evaluate their hypotheses.
    Type: Application
    Filed: June 6, 2003
    Publication date: December 9, 2004
    Applicant: Texas Instruments Incorporated
    Inventors: John G. McDonough, Gibong Jeong, Karim Abdulla, Rajiv R. Nambiar, William S. Clark
  • Publication number: 20040228268
    Abstract: System and method for intelligently and efficiently processing the results of searches for signals in a direct sequence spread spectrum communications system. A preferred embodiment comprises a search engine (for example, search engine 405) and a hardware result processor (for example, result processor 410) with a memory (for example, memory 415) as an interface. The search engine may perform multiple correlations of a pilot channel and then writes the correlation results exceeding a specified threshold to the memory. The result processor reads the correlation results from the memory and performs result filtering and builds a list of maximum value correlation results. The result processor and the search engine functions with independence from one another therefore, there is therefore, little wasted overhead where one has to wait for the other. The result filtering also makes it simpler to combine signal multipaths and simplifies pilot channel strength comparisons.
    Type: Application
    Filed: May 16, 2003
    Publication date: November 18, 2004
    Inventors: John G. McDonough, Gibong Jeong, Karim Abdulla, Rajiv R. Nambiar, William S. Clark
  • Publication number: 20040223552
    Abstract: System and method for decoding received information using batched processing of independent parameters. A preferred embodiment comprises a decoder (for example, decoder 210) with a memory (for example, memory 215) that may be partitioned into a plurality of parts, one of which being a parameter partition (for example, parameter partition 217). A digital signal processor (for example, DSP 205) programs the decoder 210 with various ways that it wishes received data to be decoded and the decoder 210 can operate independent of the DSP 205, storing the results of each decoding operation in a specified location. At specified instances, the decoder 210 interrupts the DSP 205 to allow the DSP 205 to retrieve the decoding results.
    Type: Application
    Filed: May 9, 2003
    Publication date: November 11, 2004
    Inventors: John G. McDonough, Glbong Jeong, Der-Chieh Koon
  • Publication number: 20040184567
    Abstract: System and method for decoding punctured subframes. A preferred embodiment comprises a first deinterleaver unit (for example, 5-ms deinterleaver 502) and a second deinterleaver unit (for example, 20-ms deinterleaver 504) operating in parallel, deinterleaving one symbol stream using 5- and 20-ms duration frame formats, for example. After the reception of each 5-ms subframe, the subframe is decoded in a decode unit (for example, rate matching, decoding, and CRC checking (RDC) unit 530) to verify that the subframe contains 5 ms duration frame data. If so, the subframe is noted. If all 5-ms subframes in a 20-ms duration frame contain 5-ms duration data, no decoding of results by the second deinterleaver unit is needed. If the entire 20-ms duration frame is not all 5-ms duration data, then the 5-ms duration data subframes are zeroed and the remaining data is decoded as 20-ms duration data.
    Type: Application
    Filed: March 20, 2003
    Publication date: September 23, 2004
    Inventors: John G. McDonough, Jane Wang, Gibong Jeong, Der-Chieh Koon
  • Patent number: 6771691
    Abstract: An integrated circuit including a demodulating finger is provided for variably extracting symbols in the demodulation process of spread spectrum signals. Following the uncovering of an information channel sample stream, partial I and Q accumulations are supplied at a rate of one partial I and Q accumulation per four PN chips. A dot product operation is then performed upon these partial I and Q accumulations using a pilot estimate, and the resulting partial symbols are accumulated in a second process, where the soft symbols can be selectively supplied with a symbol period in the range from 4 to 2048 PN chips. In this manner, the symbol accumulation process can be made to work with a wide variety of information channel symbol rates. A method for partially accumulating soft symbols, both before and after the dot product operation, is also provided.
    Type: Grant
    Filed: September 15, 2000
    Date of Patent: August 3, 2004
    Assignee: Texas Instruments Incorporated
    Inventor: John G. McDonough
  • Patent number: 6748006
    Abstract: Unique methods and apparatus for maintaining timing in spread spectrum communications are described. One method involves the steps of repeatedly incrementing an N-bit master binary counter at a chip rate to provide a count that rolls over at or near the end of a nominal zero-offset pseudorandom noise (PN) sequence having a length of 2N. The method includes the further steps of, for each counter of a plurality of N-bit slave binary counters, repeatedly incrementing an N-bit slave binary counter at the chip rate to generate a count that is out-of-phase with the count associated with the N-bit master binary counter by a base station offset value and a path delay value.
    Type: Grant
    Filed: May 28, 1999
    Date of Patent: June 8, 2004
    Assignees: Texas Instruments Incorporated, Koninklijke Philips Electronics N.V.
    Inventors: John G. McDonough, Tien Q. Nguyen
  • Publication number: 20040062298
    Abstract: System and method for using pipelined vector processing in the detection of direct sequence spread spectrum signals. A preferred embodiment comprises a memory (such as memory 507) used to store a plurality of hypotheses, a PN sequence generator (such as PN generator 527) that can generate PN sequences for each of the hypotheses, and vector processing correlators and accumulators (both coherent and non-coherent). The PN sequence generator can arbitrarily generate PN sequences for any hypothesis, permitting the simultaneous testing of multiple hypotheses. A searcher controller (such as search control unit 319) can schedule access to different units in a pipelined fashion to increase the number of hypotheses tested in a given period of time.
    Type: Application
    Filed: August 28, 2003
    Publication date: April 1, 2004
    Inventors: John G. McDonough, Gibong Jeong, Karim Abdulla, Rajiv R. Nambiar, William S. Clark
  • Publication number: 20040062299
    Abstract: System and method for detecting multiple direct sequence spread spectrum signals using a multi-mode searcher. A preferred embodiment comprises the specification of a hypothesis for a particular communications network. The hypothesis can then be used to generate a pseudo-random number (PN) sequence that is provided to a searcher. The searcher can then make adjustments to the PN sequence to bring the PN sequence to conformity with requirements of the particular communications network. The adjustment to the PN sequence permits the use of a multi-mode searcher to perform searches for signals of various communications networks with minimal hardware dedicated to each communications network.
    Type: Application
    Filed: August 28, 2003
    Publication date: April 1, 2004
    Inventors: John G. McDonough, Gibong Jeong, Karim Abdulla, Rajiv R. Nambiar
  • Publication number: 20040062300
    Abstract: System and method for efficient detecting of direct sequence spread spectrum signals using a searcher with batched processing. A preferred embodiment comprises a controller (such as the MCU 310) that writes sets of search parameters to a memory (such as the memory 315) to specify a group of hypotheses. A searcher (such as the searcher 305) reads the sets of search parameters from the memory and generates the groups of hypotheses from the sets of search parameters. The searcher then assigns the hypotheses to correlators and tests each of the hypotheses. Results from the testing can be written back to the memory.
    Type: Application
    Filed: September 11, 2003
    Publication date: April 1, 2004
    Inventors: John G. McDonough, Gibong Jeong, Karim Abdulla, Rajiv R. Nambiar, William S. Clark
  • Publication number: 20040062297
    Abstract: System and method for performing symbol boundary aligned searches of signals. A preferred embodiment comprises a search control unit (such as search control unit 725) that can determine a start and stop condition for a correlation based on a hypothesis, a searcher (such as searcher 705) which includes a multiplexer that can select a subset of samples of a received sequence based on the hypothesis and start and stop conditions. The search control unit can then wait for the occurrence of the start condition and assign the hypothesis to a correlator, which will correlate the subset of samples with a locally generated pseudo-random number sequence based upon the hypothesis.
    Type: Application
    Filed: August 28, 2003
    Publication date: April 1, 2004
    Inventors: John G. McDonough, Gibong Jeong, Karim Abdulla, Rajiv R. Nambiar
  • Patent number: 6658042
    Abstract: A method of providing time tracking between a first signal and a second signal in a communication device. In one embodiment, a first signal is generated by the communication device and a second signal is received from an outside source. Then correlation data between a first signal, at a plurality of timing conditions, and a second signal is generated by hardware. Next, the correlation data is filtered by software or firmware at a plurality of timing conditions. Afterward, the correlation data is compared to a threshold value to evaluate accuracy of a system timing for the first signal to obtain a result. Finally, the system timing for the first signal is corrected based upon said result of the comparing step.
    Type: Grant
    Filed: September 24, 1999
    Date of Patent: December 2, 2003
    Assignee: Koninklijke Philips Electronics N.V.
    Inventors: Howard (Hau) Thien Tran, John G. McDonough
  • Patent number: 6654405
    Abstract: A processing apparatus for use in spread spectrum communications includes a controller, a filter programmed in the controller, and a dot product hardware unit external from the controller having the programmed filter. The controller provides a filter input to receive I and Q pilot symbols and a filter output to provide I and Q pilot symbol estimates based on the I and Q pilot signals. The dot product hardware unit has a first input coupled to receive the I and Q pilot symbol estimates, a second input coupled to receive I and Q data symbols, and an output to provide results of a dot product function between the I and Q pilot symbol estimates and the I and Q data symbols.
    Type: Grant
    Filed: October 19, 2000
    Date of Patent: November 25, 2003
    Assignee: Texas Instruments Incorporated
    Inventor: John G. McDonough
  • Patent number: 6650687
    Abstract: One particular data sequence generator for spread spectrum communications includes a first data access module, a second data access module, and a binary counter for use in repeatedly providing counter values from 0 to 215−1 at a 15-bit output. The first data access module, which may include a read-only memory (ROM), has first and second pseudorandom noise (PN) sequences encoded therein, each having a length of 215. The first data access module has a 15-bit input coupled to the 15-bit output providing the counter values. The first, data access module also has a first bit output to provide a selected PN bit of the first PN sequence and a second bit output to provide a selected PN bit of the second PN sequence responsive to each one of the counter values from 0 to 215−1. The second data access module, which may also include a ROM, has an N-bit input coupled to N lines of the 15-bit output.
    Type: Grant
    Filed: October 19, 2000
    Date of Patent: November 18, 2003
    Assignee: Texas Instruments Incorporated
    Inventor: John G. McDonough
  • Patent number: 6625199
    Abstract: Inventive methods and apparatus for use in simultaneously generating two or more pseudorandom noise (PN) sequences for spread spectrum communications are described. A data sequence generator includes a data access module and a multiplexing device. The multiplexing device has inputs to receive first counter values associated with a first demodulator and second counter values associated with a second demodulator. The multiplexing device has an output to provide, in an interleaved fashion, the first counter values and the second counter values to an input to the data access module. An output from the data access module provides, in an interleaved fashion, PN sequence data responsive to the first counter values and PN sequence data responsive to the second counter values for the first and the second demodulators, respectively. Preferably the data access module is a read-only memory (ROM) having the PN sequence stored therein.
    Type: Grant
    Filed: October 19, 2000
    Date of Patent: September 23, 2003
    Assignee: Texas Instruments Incorporated
    Inventor: John G. McDonough
  • Publication number: 20030156593
    Abstract: A CDMA receiver (500) minimizes the use of hardware by taking advantage of the fact that Walsh sequences of a predetermined length (e.g., 16) are comprised of inverted and non-inverted versions of smaller length (e.g., 4) sequences. The receiver (500) performs the necessary uncovering operations for example of a Walsh sequence of length 16 by performing uncovering operations using smaller length Walsh sequences such as of length 4 and then performing subsequent summing operations with inverted and non-inverted versions of the results of such uncovering operations.
    Type: Application
    Filed: February 19, 2003
    Publication date: August 21, 2003
    Inventors: John G. McDonough, Jane Wang
  • Publication number: 20030156627
    Abstract: A demodulator such as a Fast Hadamard Transform (FHT) based demodulator is used to demodulate all channels in a code space with code length equal to the data channel code. Since the codes for overhead control channels are usually longer, the control channel data is only partially uncovered. Once the necessary further processing is performed and the information to fully uncover the control channels is available, the control channel data is fully demodulated. By only processing one partially uncovered secondary control channel, the present invention reduces the implementation complexity. A hardware implementation of the above method, requires fewer data processing operations, and reduces data processing delays, resulting in lower power consumption.
    Type: Application
    Filed: May 28, 2002
    Publication date: August 21, 2003
    Inventors: John G. McDonough, Jane Wang, Yan Hui
  • Publication number: 20030118050
    Abstract: A vector-based sequence generator (100) provides for a general architecture that can be easily adapted to any random length sequence and any random number of bits per access. The sequence generator (100) can also produce a new access on every hardware clock cycle, thereby maximizing the efficiency of the bit sequence requesting process.
    Type: Application
    Filed: April 11, 2002
    Publication date: June 26, 2003
    Inventors: John G. McDonough, Douglas R. Walby, Karim Abdulla
  • Publication number: 20030117942
    Abstract: A vector-based Walsh code sequence generator (100) provides for a general architecture that can be easily adapted to any random length sequence and any random number of bits per access. The Walsh code sequence generator (100) can produce a new access on every hardware clock cycle, thereby maximizing the efficiency of the bit sequence requesting process.
    Type: Application
    Filed: April 11, 2002
    Publication date: June 26, 2003
    Inventors: John G. McDonough, Douglas R. Walby, Karim Abdulla
  • Publication number: 20030108086
    Abstract: A method and apparatus for interleaving multiple frames of data as disclosed provide for an extremely streamlined approach to achieving both methods of interleaving as defined in the IS-2000 standard while meeting the complex requirement of frame puncturing. Output addressing is directly driven by a PN index or a counter locked to the reverse link timing, it is a simple manner of range selection to achieve all possible configurations required in the IS-2000 standard. Puncturing of sub-20 ms frames is also easily accomplished by using a single contiguous memory and interleaver engine that resides in the input side of the interleaver memory.
    Type: Application
    Filed: December 6, 2001
    Publication date: June 12, 2003
    Inventors: Peter Rastello, John G. McDonough
  • Patent number: 6559714
    Abstract: A signal filter employs digital control signals to selectively establish and adjust analog impedance components of the filter. In the case of a first-order R-C filter, adjustable resistance and reactance assemblies are coupled in series. The resistance assembly has multiple parallel signal paths sharing a common input and output. Each signal path includes a prescribed electrical resistance and a digital switch to selectively enable and disable the resistance. Between the common input and output, the signal paths provide a collective resistance which varies depending upon which switches have been activated. The reactance assembly is similar to the resistance assembly, with capacitors or inductors instead of resistors. A digital controller selectively activates the switches to adjust the assemblies' respective resistance and reactance.
    Type: Grant
    Filed: March 28, 2001
    Date of Patent: May 6, 2003
    Assignee: Texas Instruments Incorporated
    Inventors: Edwin Park, John G. McDonough