Patents by Inventor John H. Lau
John H. Lau has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 9252054Abstract: A thinned integrated circuit device and manufacturing process for the same are disclosed. The manufacturing process includes forming a through-silicon via (TSV) on a substrate, a first terminal of the TSV is exposed on a first surface of the substrate, disposing a bump on the first surface of the substrate to make the bump electrically connected with the TSV, disposing an integrated circuit chip (IC) on the bump so that a first side of the IC is connected to the bump, disposing a thermal interface material (TIM) layer on a second side of the IC opposite to the first side of the IC, attaching a heat-spreader cap on the IC by the TIM layer, and backgrinding a second surface of the substrate to expose the TSV to the second surface of the substrate while carrying the heat-spreader cap.Type: GrantFiled: September 12, 2014Date of Patent: February 2, 2016Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Sheng-Tsai Wu, Heng-Chieh Chien, John H. Lau, Yu-Lin Chao, Wei-Chung Lo
-
Publication number: 20150076682Abstract: A thinned integrated circuit device and manufacturing process for the same are disclosed. The manufacturing process includes forming a through-silicon via (TSV) on a substrate, a first terminal of the TSV is exposed on a first surface of the substrate, disposing a bump on the first surface of the substrate to make the bump electrically connected with the TSV, disposing an integrated circuit chip (IC) on the bump so that a first side of the IC is connected to the bump, disposing a thermal interface material (TIM) layer on a second side of the IC opposite to the first side of the IC, attaching a heat-spreader cap on the IC by the TIM layer, and backgrinding a second surface of the substrate to expose the TSV to the second surface of the substrate while carrying the heat-spreader cap.Type: ApplicationFiled: September 12, 2014Publication date: March 19, 2015Inventors: Sheng-Tsai WU, Heng-Chieh CHIEN, John H. LAU, Yu-Lin CHAO, Wei-Chung LO
-
Patent number: 8673658Abstract: A fabricating method and a testing method of a semiconductor device and a mechanical integrity testing apparatus are provided. An object includes a wafer, an insulating layer, and a plurality of conductive posts is provided. A surface of the wafer has a plurality of first blind holes outside chip regions and a plurality of second blind holes inside the chip regions. The insulating layer is between the conductive posts and the walls of the first blind holes and between the conductive posts and the walls of the second blind holes. A mechanical integrity test is performed to test a binding strength between the insulating layer, the conductive posts, and the walls of the first blind holes. The conductive posts in the chip regions are electrically connected to an element after the conductive posts in the first blind holes are qualified in the mechanical integrity test.Type: GrantFiled: February 19, 2013Date of Patent: March 18, 2014Assignee: Industrial Technology Research InstituteInventors: Ming-Che Hsieh, John H. Lau, Ra-Min Tain
-
Patent number: 8674491Abstract: A semiconductor device including a silicon substrate, a plurality of silicon nanowire clusters, a first circuit layer and a second circuit layer. The silicon substrate has a first surface, a second surface opposite to the first surface and a plurality of through holes. The silicon nanowire clusters are disposed in the through holes of the silicon substrate, respectively. The first circuit layer is disposed on the first surface and connected to the silicon nanowire clusters. The second circuit layer is disposed on the second surface and connected to the silicon nanowire clusters.Type: GrantFiled: May 9, 2011Date of Patent: March 18, 2014Assignee: Industrial Technology Research InstituteInventors: Chun-Kai Liu, John H. Lau, Ming-Ji Dai, Ra-Min Tain
-
Patent number: 8536701Abstract: An electronic device packaging structure is provided. The semiconductor device includes a semiconductor base, an emitter, a collector, and a gate. The emitter and the gate are disposed on a first surface of the semiconductor base. The collector is disposed on a second surface of the semiconductor base. A first passivation layer is located on the first surface of the semiconductor base surrounding the gate. A first conductive pad is disposed on the first passivation layer. A second conductive pad is disposed on the collector on the second surface. At least one conductive through via structure penetrates the first passivation layer, the first and second surfaces of the semiconductor base, and the collector to electrically connect the first and second conductive pads.Type: GrantFiled: March 5, 2012Date of Patent: September 17, 2013Assignee: Industrial Technology Research InstituteInventors: Ra-Min Tain, Ming-Ji Dai, John H. Lau
-
Patent number: 8519524Abstract: A chip stacking structure including a carrier, a first redistribution layer, a second redistribution layer, at least one first chip, at least one second chip, and at least one conductor is provided. The carrier has a first surface and a second surface opposite to each other. The carrier has at least one through hole. The first and second redistribution layers are disposed on the first and second surfaces of the carrier, respectively. The first and second chips are disposed on the first and second surfaces of the carrier and electrically connected with the first and second redistribution layers, respectively. The conductor is disposed on one of the first and second chips. The conductor is disposed in the through hole. The first and second chips are electrically connected by the conductor. A gap is formed between the conductor and an inner wall of the carrier which surrounds the through hole.Type: GrantFiled: August 16, 2012Date of Patent: August 27, 2013Assignee: Industrial Technology Research InstituteInventors: Sheng-Tsai Wu, John H. Lau, Heng-Chieh Chien, Ra-Min Tain, Ming-Ji Dai, Yu-Lin Chao
-
Measuring apparatus that includes a chip having a through silicon via, a heater, and a stress sensor
Patent number: 8502224Abstract: A measuring apparatus including a first chip, a first circuit layer, a first heater, a first stress sensor and a second circuit layer is provided. The first chip has a first through silicon via, a first surface and a second surface opposite to the first surface. The first circuit layer is disposed on the first surface. The first heater and the first stress sensor are disposed on the first surface and connected to the first circuit layer. The second circuit layer is disposed on the second surface.Type: GrantFiled: December 8, 2010Date of Patent: August 6, 2013Assignee: Industrial Technology Research InstituteInventors: Ra-Min Tain, John H. Lau, Ming-Che Hsieh, Wei Li, Ming-Ji Dai -
Patent number: 8456017Abstract: By adding particles of high thermal conductivity and low thermal expansion coefficient into the copper as a composite material and filling with the composite material into the through-via hole, the mismatch of the coefficient of thermal expansion and the stress of the through-silicon via are lowered and the thermal conductivity of the through-silicon via is increased.Type: GrantFiled: July 1, 2011Date of Patent: June 4, 2013Assignee: Industrial Technology Research InstituteInventors: Ming-Ji Dai, Heng-Chieh Chien, Ming-Che Hsieh, Jui-Feng Hung, Ra-Min Tain, John H. Lau
-
Patent number: 8397584Abstract: A fabricating method and a testing method of a semiconductor device and a mechanical integrity testing apparatus are provided. An object includes a wafer, an insulating layer, and a plurality of conductive posts is provided. A surface of the wafer has a plurality of first blind holes outside chip regions and a plurality of second blind holes inside the chip regions. The insulating layer is between the conductive posts and the walls of the first blind holes and between the conductive posts and the walls of the second blind holes. A mechanical integrity test is performed to test a binding strength between the insulating layer, the conductive posts, and the walls of the first blind holes. The conductive posts in the chip regions are electrically connected to an element after the conductive posts in the first blind holes are qualified in the mechanical integrity test.Type: GrantFiled: February 9, 2011Date of Patent: March 19, 2013Assignee: Industrial Technology Research InstituteInventors: Ming-Che Hsieh, John H. Lau, Ra-Min Tain
-
Publication number: 20120322249Abstract: In a manufacturing method of a semiconductor structure, a substrate having a front surface and a back surface is provided. The front surface has a device layer thereon and conductive plugs electrically connected to the device layer. A thinning process is performed on the back surface of the substrate, such that the back surface of the substrate and surfaces of the conductive plugs have a distance therebetween. Holes are formed in the substrate from the back surface to the conductive plugs, so as to form a porous film. An oxidization process is performed, such that the porous film correspondingly is reacted to form an oxide material layer. A polishing process is performed on the oxide material layer to expose the surfaces of the conductive plugs.Type: ApplicationFiled: August 28, 2012Publication date: December 20, 2012Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Jui-Chin Chen, Cha-Hsin Lin, John H. Lau, Tzu-Kun Ku
-
Publication number: 20120280385Abstract: An electronic device packaging structure is provided. The semiconductor device includes a semiconductor base, an emitter, a collector, and a gate. The emitter and the gate are disposed on a first surface of the semiconductor base. The collector is disposed on a second surface of the semiconductor base. A first passivation layer is located on the first surface of the semiconductor base surrounding the gate. A first conductive pad is disposed on the first passivation layer. A second conductive pad is disposed on the collector on the second surface. At least one conductive through via structure penetrates the first passivation layer, the first and second surfaces of the semiconductor base, and the collector to electrically connect the first and second conductive pads.Type: ApplicationFiled: March 5, 2012Publication date: November 8, 2012Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Ra-Min Tain, Ming-Ji Dai, John H. Lau
-
Publication number: 20120273939Abstract: By adding particles of high thermal conductivity and low thermal expansion coefficient into the copper as a composite material and filling with the composite material into the through-via hole, the mismatch of the coefficient of thermal expansion and the stress of the through-silicon via are lowered and the thermal conductivity of the through-silicon via is increased.Type: ApplicationFiled: July 1, 2011Publication date: November 1, 2012Applicant: Industrial Technology Research InstituteInventors: Ming-Ji Dai, Heng-Chieh Chien, Ming-Che Hsieh, Jui-Feng Hung, Ra-Min Tain, John H. Lau
-
Publication number: 20120249176Abstract: A test structure including a substrate, at least one conductive plug, a first conductive trace and a second conductive trace is provided. The substrate has a first area and a second area. The at lest one conductive plug is disposed in the substrate in the first area, wherein the conductive plug does not penetrate through the substrate. The first conductive trace is disposed on the conductive plug and on the substrate in the first area. The second conductive trace is disposed on the substrate in the second area. It is noted that the first conductive trace and the second conductive trace have the same material and the same shape. A measurement method of the above-mentioned test structure is also provided.Type: ApplicationFiled: June 27, 2011Publication date: October 4, 2012Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Heng-Chieh Chien, Ra-Min Tain, John H. Lau, Yu-Lin Chao, Ming-Ji Dai
-
Publication number: 20120153454Abstract: A semiconductor device including a silicon substrate, a plurality of silicon nanowire clusters, a first circuit layer and a second circuit layer. The silicon substrate has a first surface, a second surface opposite to the first surface and a plurality of through holes. The silicon nanowire clusters are disposed in the through holes of the silicon substrate, respectively. The first circuit layer is disposed on the first surface and connected to the silicon nanowire clusters. The second circuit layer is disposed on the second surface and connected to the silicon nanowire clusters.Type: ApplicationFiled: May 9, 2011Publication date: June 21, 2012Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Chun-Kai Liu, John H. Lau, Ming-Ji Dai, Ra-Min Tain
-
Publication number: 20120135547Abstract: A fabricating method and a testing method of a semiconductor device and a mechanical integrity testing apparatus are provided. An object includes a wafer, an insulating layer, and a plurality of conductive posts is provided. A surface of the wafer has a plurality of first blind holes outside chip regions and a plurality of second blind holes inside the chip regions. The insulating layer is between the conductive posts and the walls of the first blind holes and between the conductive posts and the walls of the second blind holes. A mechanical integrity test is performed to test a binding strength between the insulating layer, the conductive posts, and the walls of the first blind holes. The conductive posts in the chip regions are electrically connected to an element after the conductive posts in the first blind holes are qualified in the mechanical integrity test.Type: ApplicationFiled: February 9, 2011Publication date: May 31, 2012Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Ming-Che Hsieh, John H. Lau, Ra-Min Tain
-
Publication number: 20120133046Abstract: A semiconductor structure and a process thereof are provided. The semiconductor structure includes a semiconductor wafer having a first surface and a second surface opposite to the first surface, through silicon vias and a crack stopping slot. The through silicon vias are embedded in the semiconductor wafer and connected between the first surface and the second surface. The crack stopping slot is located in the periphery of the second surface of the semiconductor wafer. The depth of the crack stopping slot is less than or equal to the thickness of the semiconductor wafer. The process firstly provides a semiconductor wafer having through silicon vias. Then, the aforementioned crack stopping slot is formed at a back side of the semiconductor wafer opposite to the first surface. Next, the semiconductor wafer is thinned from the back side to expose a second end of each through silicon via.Type: ApplicationFiled: March 1, 2011Publication date: May 31, 2012Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Chun-Hsien Chien, John H. Lau, Hsiang-Hung Chang, Huan-Chun Fu, Tzu-Ying Kuo, Wen-Li Tsai
-
Publication number: 20120119375Abstract: In a manufacturing method of a semiconductor structure, a substrate having a front surface and a back surface is provided. The front surface has a device layer thereon and conductive plugs electrically connected to the device layer. A thinning process is performed on the back surface of the substrate, such that the back surface of the substrate and surfaces of the conductive plugs have a distance therebetween. Holes are formed in the substrate from the back surface to the conductive plugs, so as to form a porous film. An oxidization process is performed, such that the porous film correspondingly is reacted to form an oxide material layer. A polishing process is performed on the oxide material layer to expose the surfaces of the conductive plugs.Type: ApplicationFiled: December 14, 2010Publication date: May 17, 2012Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Jui-Chin Chen, Cha-Hsin Lin, John H. Lau, Tzu-Kun Ku
-
Publication number: 20120018723Abstract: A test structure including at least one ground pad, an input pad, at least one first through-silicon via (TSV), at least one second TSV and an output pad is disclosed. The ground pad receives a ground signal during a test mode. The input pad receives a test signal during the test mode. The first TSV is coupled to the input pad. The output pad is coupled to the second TSV. No connection line occurs between the first and the second TSVs. During the test mode, a test result is obtained according to the signal of at least one of the first and the second TSVs, and structural characteristics can be obtained according to the test result.Type: ApplicationFiled: December 14, 2010Publication date: January 26, 2012Inventors: Keng-Li SU, Chih-Sheng Lin, Wen-Pin Lin, John H. Lau
-
Publication number: 20110309357Abstract: A measuring apparatus including a first chip, a first circuit layer, a first heater, a first stress sensor and a second circuit layer is provided. The first chip has a first through silicon via, a first surface and a second surface opposite to the first surface. The first circuit layer is disposed on the first surface. The first heater and the first stress sensor are disposed on the first surface and connected to the first circuit layer. The second circuit layer is disposed on the second surface.Type: ApplicationFiled: December 8, 2010Publication date: December 22, 2011Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Ra-Min Tain, John H. Lau, Ming-Che Hsieh, Wei Li, Ming-Ji Dai
-
Patent number: 6299058Abstract: A method for positioning a solder ball onto a contact tail of an electrical connector comprises several steps. Firstly, arrange the contact tail into a center region and a peripheral region surrounding the center region. Secondly, attach solder paste onto the center region of the contact tail via a first mesh painting procedure. Thirdly, attach solder resist onto the peripheral region of the contact tail via a second mesh painting procedure. Fourthly, position a solder ball on the center region of the contact tail via a screen board. Fifthly, apply a reflow soldering procedure on the solder ball so that the solder ball can be soldered on the solder paste attached to the center region of the contact tail.Type: GrantFiled: April 30, 1999Date of Patent: October 9, 2001Assignee: Hon Hai Precision Ind. Co., Ltd.Inventors: John H. Lau, Scott Lin, Ming-Lun Szu