Abstract: Integrated circuits (ICs), including capacitors and inductors, employing directly coupled metal lines between vertically-adjacent interconnect layers for reduced coupling resistance, and related fabrication methods. By directly coupled, it is meant that there is not an intermediate vertical interconnect access (via) layer with a via(s) interconnecting the metal lines in vertically-adjacent interconnect layers. An overlying and underlying metal line in respective and vertically-adjacent overlying and underlying interconnect layers are directly coupled to each other without the need for an intermediate via layer. For example, directly coupled metal in adjacent interconnect layers of IC can reduce contact resistance between the metal lines and reduce the overall height of the IC.

Abstract: An interconnect structure comprising a low via resistance via structure is disclosed. The via structure comprises a barrier layer on sidewalls and at bottom of the via structure. The interconnect structure also includes a first metal layer. The interconnect structure further includes a second metal layer between the barrier layer at the bottom of the via structure and the first metal layer, wherein the first metal layer and the second metal layer comprise different materials.

Abstract: Integrated circuits (ICs), including capacitors and inductors, employing directly coupled metal lines between vertically-adjacent interconnect layers for reduced coupling resistance, and related fabrication methods. By directly coupled, it is meant that there is not an intermediate vertical interconnect access (via) layer with a via(s) interconnecting the metal lines in vertically-adjacent interconnect layers. An overlying and underlying metal line in respective and vertically-adjacent overlying and underlying interconnect layers are directly coupled to each other without the need for an intermediate via layer. For example, directly coupled metal in adjacent interconnect layers of lC can reduce contact resistance between the metal lines and reduce the overall height of the IC.

Abstract: Disclosed are examples of a device and method of fabricating a device including a first top contact, a second top contact, adjacent the first top contact, a first mesa disposed below the first top contact and a second mesa disposed below the second top contact. A first plate of a metal-insulator-metal (MIM) capacitor is disposed below the first top contact and electrically coupled to the first top contact. A first insulator of the MIM capacitor is disposed on the first plate. A second plate of the MIM capacitor is disposed on the first insulator and electrically coupled to the second top contact. A second insulator of the MIM capacitor is disposed on the second plate. A third plate of the MIM capacitor is disposed on the second insulator and electrically coupled to the first top contact.

Abstract: Disclosed are apparatuses including a transistor cell and methods of fabricating the transistor cell. The transistor cell may include a substrate, an active region and a gate having a gate contact in the active region. The transistor cell may further include a first portion of a spacer of the gate contact formed from a first material, and a second portion of the spacer of the gate contact formed from a second material.

Abstract: A metal oxide metal (MOM) capacitor and methods for fabricating the same are disclosed. The MOM capacitor includes a first metal layer having a first plurality of fingers, each of the first plurality of fingers configured to have alternating polarities. A high resistance (Hi-R) conductor layer is disposed adjacent the first metal layer in a plane parallel to the first metal layer.

Abstract: In an aspect, a system on a chip (SOC) includes a plurality of function blocks, including a first function block and a second function block, co-located on the SOC. The SOC includes a first metal layer, a first dielectric layer located on top of the first metal layer, and a first via located in the first dielectric layer and used in the first function block. The SOC includes a second via located in the first dielectric layer and used in the second function block and a second metal layer located on the first dielectric layer. The second metal layer comprises a first set of connections used in the first function block and a second set of connections used in the second function block. The first set of connections is different from the second set of connections. The SOC includes a second dielectric layer located on the first dielectric layer.

Abstract: An integrated circuit (IC) having an interconnect structure with metal lines with different conductive materials for different widths and a method for fabricating such an IC. An example IC generally includes an active layer and an interconnect structure disposed thereabove and comprising a plurality of metal layers and one or more vias landing on metal lines. At least one of the plurality of metal layers comprises one or more first metal lines and one or more second metal lines. The one or more first metal lines have one or more first widths and comprise a first conductive material including copper. The one or more second metal lines have one or more second widths and comprise a second conductive material different from the first conductive material, where the second widths are narrower than the first widths. The vias have one or more third widths and comprise a third conductive material.

Abstract: Disclosed are standard cells and methods for fabricating standard cells used in semiconductor device design and fabrication. Aspects disclosed include a standard cell having a plurality of wide metal lines. The wide metal lines being formed from copper. The standard cell also includes a plurality of narrow metal lines. The narrow metal lines are formed from a material that has a lower resistance than copper for line widths on the order of twelve nanometers or less.

Abstract: Certain aspects of the present disclosure generally relate to integration of a hybrid conductor material in power rails of a semiconductor device. An example semiconductor device generally includes an active electrical device and a power rail. The power rail is electrically coupled to the active electrical device, disposed above the active electrical device, and embedded in at least one dielectric layer. The power rail includes a first conductive layer, a barrier layer, and a second conductive layer. In certain cases, copper may be used as conductive material for the second conductive layer. The barrier layer is disposed between the first conductive layer and the second conductive layer.

Abstract: Disclosed are examples of interconnect structures, e.g., in semiconductor packages. The interconnect structures may include metal lines with graphene. Graphene aids in reducing resistivity of metals used in interconnects. Graphene also serves as diffusion barriers. These properties are advantages when critical dimensions of conductive structures are reduced.

Abstract: Certain aspects of the present disclosure generally relate to a metal-oxide-metal (MOM) capacitor formed from a subtractive back-end-of-line (BEOL) scheme. One example method of fabricating a semiconductor device generally includes forming an active layer and forming a capacitive element above the active layer with a back-end-of-line subtractive process for conductive materials.

Abstract: Certain aspects of the present disclosure generally relate to a metal-oxide-metal (MOM) capacitor formed from a subtractive back-end-of-line (BEOL) scheme. One example method of fabricating a semiconductor device generally includes forming an active layer and forming a capacitive element above the active layer with a back-end-of-line subtractive process for conductive materials.

Abstract: Cell circuits formed in circuit cells employing offset gate cut areas in a non-active area for routing transistor gate cross-connections. In exemplary aspects disclosed herein, to allow cross-connections to be made across different gates between PMOS and NMOS transistors formed in the circuit cell, cut areas in the circuit cell are located in different horizontal routing tracks and offset from each other in the direction of longitudinal axes of gates. Gate cross-connections can be routed around offset gate cut areas and coupled to active gates to form gate cross-connections. In this manner, fewer metal layers may be required to provide such cross-connections in the circuit cell, thus reducing area. Further, gate contacts of cross-connected gates can be formed as gate contacts over active areas (GCOAs) in diffusion areas of the circuit cell, thus facilitating easier routing of interconnections in non-diffusion area of the circuit cell for further ease of routing.

Abstract: Certain aspects of the present disclosure generally relate to a hybrid back-end-of-line (BEOL) dielectric for a high capacitance density metal-oxide-metal (MOM) capacitor, especially in lower BEOL layers. One example semiconductor device includes an active layer and a first metal layer disposed above the active layer. The first metal layer generally includes: a first electrode; a second electrode, wherein the first and second electrodes have interdigitated fingers; a first dielectric material disposed at least partially between at least two adjacent fingers of the first and second electrodes; and a second dielectric material, wherein the second dielectric material is different from the first dielectric material and wherein the first electrode, the second electrode, and the first dielectric material compose a portion of a metal-oxide-metal (MOM) capacitor.

Abstract: The parasitic capacitance of a transistor may be reduced by mismatching the source and drain. Faster low finger count transistors may be achieved with lower drain capacitance and a frequency gain on the D1 inverter as described for the examples herein. In one such example, a transistor includes a source and a drain wherein a length of the source is more than a length of the drain, a width of the source is more than a width of the drain, or a height of the source is more than a height of the drain.

Abstract: Certain aspects of the present disclosure generally relate to integration of a hybrid conductor material in power rails of a semiconductor device. An example semiconductor device generally includes an active electrical device and a power rail. The power rail is electrically coupled to the active electrical device, disposed above the active electrical device, and embedded in at least one dielectric layer. The power rail comprises a first conductive layer, a barrier layer, and a second conductive layer comprising copper. The barrier layer is disposed between the first conductive layer and the second conductive layer.

Abstract: A cell circuit includes a first power rail, having a first line length, in a first layer. The first power rail is configured to receive a first voltage for the cell circuit. The cell circuit includes multiple lines in a second layer and a shunt in a third layer. The shunt is electrically coupled to the first power rail and a first set of lines of the multiple lines. The shunt has a second line length shorter than the first line length. The cell circuit includes another shunt in t the third layer. The other shunt is also parallel to the first power rail. The other shunt is electrically coupled to the first power rail and a second set of lines of the multiple lines. The other shunt has a third line length shorter than the first line length.

Abstract: Disclosed are standard cells and methods for fabricating standard cells used in semiconductor device design and fabrication. Aspects disclosed include a standard cell having a plurality of wide metal lines. The wide metal lines being formed from copper. The standard cell also includes a plurality of narrow metal lines. The narrow metal lines are formed from a material that has a lower resistance than copper for line widths on the order of twelve nanometers or less.

Abstract: Certain aspects of the present disclosure generally relate to methods of fabricating integrated circuits. An example method generally includes forming a first cavity in a first layer disposed above a second layer and filling at least a portion of the first cavity with a dielectric material disposed above the second layer. The method further includes forming a second cavity in the dielectric material such that the dielectric material remaining in the first cavity is disposed on (e.g., conforms to) lateral surfaces of the first layer in the first cavity and forming a dielectric spacer comprising a segment of the remaining dielectric material in the first cavity. The method also includes forming a first conductor, in the first layer or the second layer, that is laterally spaced from a second conductor based at least in part on a width of the dielectric spacer.