Abstract: Systems and methods for monitoring a number of operating conditions of a programmable device are disclosed. In some implementations, the system may include a root monitor including circuitry configured to generate a reference voltage, a plurality of sensors and satellite monitors distributed across the programmable device, and a interconnect system coupled to the root monitor and to each of the plurality of satellite monitors. Each of the satellite monitors may be in a vicinity of and coupled to a corresponding one of the plurality of sensors via a local interconnect. The interconnect system may include one or more analog channels configured to distribute the reference voltage to each of the plurality of satellite monitors, and may include one or more digital channels configured to selectively route digital data from each of the plurality of satellite monitors to the root monitor as data packets.

Abstract: Method and apparatus for sharing an analog signal for use by a plurality of devices are disclosed. In some implementations, the analog signal may be generated by a controller. The controller also may generate a control signal to determine when other devices use the analog signal. In one implementation, the control signal may be a token that may be transmitted and received by the other devices. If a device possess the token, then the device may use the analog signal. If the device does not possess the token, then the device may not use the analog signal. In another implementation, the controller may transmit a peer-to-peer message to a selected device. When the selected device receives the peer-to-peer message, then the selected device may use the analog signal. In this manner, the controller ensures that only one device at a time may use the analog signal.

Abstract: Systems and methods for monitoring a number of operating conditions of a programmable device are disclosed. In some implementations, the system may include a root monitor including circuitry configured to generate a reference voltage, a plurality of sensors and satellite monitors distributed across the programmable device, and a network-on-chip (NoC) interconnect system coupled to the root monitor and to each of the plurality of satellite monitors. Each of the satellite monitors may be in a vicinity of and coupled to a corresponding one of the plurality of sensors via a local interconnect.

Abstract: A temperature sensor includes a current source to produce a first bias current and a second bias current, a plurality of diodes, and temperature estimation circuitry. The plurality of diodes includes at least a first diode to receive the first bias current and a second diode to receive the second bias current. The temperature estimate circuitry measures a first voltage bias across the first diode resulting from the first bias current and a second voltage bias across the second diode resulting from the second bias current, and estimates a temperature of an environment of the temperature sensor based at least in part on the first voltage bias and the second voltage bias. The temperature sensor further includes error detection circuitry to measure at least one of the first or second bias currents and determine an amount of error in the temperature estimate based at least in part on the measurement.

Abstract: Examples described herein provide a circuit and methods for self-testing to detect damage to a device, which damage may be caused by an Electro-Static Discharge (ESD) event. In an example, an integrated circuit includes an input/output circuit, an ESD protection circuit, and a system monitor. The input/output circuit has an input/output node. The ESD protection circuit is connected to the input/output node. The system monitor has a driving/measurement node selectively connectable to the input/output node. The system monitor is configured to drive and measure a voltage of the driving/measurement node. The system monitor is further configured to determine, based on driving and measuring the voltage of the driving/measurement node, whether a damaged device is present. The damaged device is in the input/output circuit or the ESD protection circuit.

Abstract: Method and apparatus for monitoring and reconfiguring a programmable device are disclosed. In some implementations, the programmable device may include a processor and a plurality of satellite monitors to determine operating temperatures at various locations throughout the programmable device. When temperatures of at least some of the satellite monitors exceed a threshold, the processor may reconfigure the programmable device using an alternative configuration. The alternative configuration may provide equivalent functionality with respect to an initial configuration through a different arrangement of functional blocks within the programmable device. The new arrangement of functional blocks may reduce operating temperatures by relocating blocks to different regions of the programmable device.

Abstract: Systems and methods for monitoring a number of operating conditions of a programmable device are disclosed. In some implementations, the system may include a root monitor including circuitry configured to generate a reference voltage, a plurality of sensors and satellite monitors distributed across the programmable device, and a interconnect system coupled to the root monitor and to each of the plurality of satellite monitors. Each of the satellite monitors may be in a vicinity of and coupled to a corresponding one of the plurality of sensors via a local interconnect. The interconnect system may include one or more analog channels configured to distribute the reference voltage to each of the plurality of satellite monitors, and may include one or more digital channels configured to selectively route digital data from each of the plurality of satellite monitors to the root monitor as data packets.

Abstract: Apparatus and associated methods relate to a circuit that is configured to keep a comparator input voltage stable. In an illustrative example, the circuit may include a first differential path coupled to a first switched-capacitor network's output, a second differential path coupled to a second switched-capacitor network's output. A comparator may have a first input coupled to the first differential path and a second input coupled to the second differential path. The comparator may be controlled by a clock signal to perform comparison. A first capacitor may be coupled from the clock signal to the first differential signal path and a second capacitor may be coupled from the clock signal to the second differential signal path. By introducing the first capacitor and the second capacitor, the comparator input common-mode may keep stable, and the comparator may be less sensitive to kickback effects.

Abstract: Systems and methods for monitoring operating conditions of a programmable device are disclosed. The system may include a root monitor configured to generate a reference voltage, a plurality of sensors distributed across the device, and a plurality of satellite monitors distributed across the device. Each of the satellite monitors may be coupled to a corresponding sensor via a local interconnect, and may be configured to convert analog signals generated by the sensor into digital data indicative of one or more operating conditions of an associated circuit. In some implementations, each satellite monitor may include a circuit to store a local reference voltage, an analog-to-digital converter (ADC) to convert the analog signals into digital codes, a calibration circuit to generate a correction factor indicative of errors in the digital codes, and a correction circuit to correct the digital codes based on the correction factor.

Abstract: A complementary metal-oxide-semiconductor (CMOS) switching system with increased supply rejection is disclosed. The system comprises a voltage regulator and a CMOS circuit. The voltage regulator receives a supply voltage and generates a regulated voltage by regulating an amplitude of the received supply voltage. The CMOS circuit includes an input terminal to receive a first voltage, switching circuitry to selectively couple the CMOS circuit to the voltage regulator in one of a plurality of configurations, and an output terminal to output a second voltage based at least in part on the first voltage and the regulated voltage when the CMOS circuit is coupled to the voltage regulator in a first configuration of the plurality of configurations.

Abstract: Systems and methods for monitoring a number of operating conditions of a programmable device are disclosed. In some implementations, the system may include a root monitor including circuitry configured to generate a reference voltage, a plurality of sensors and satellite monitors distributed across the programmable device, and a network-on-chip (NoC) interconnect system coupled to the root monitor and to each of the plurality of satellite monitors. Each of the satellite monitors may be in a vicinity of and coupled to a corresponding one of the plurality of sensors via a local interconnect.

Abstract: An example dynamic element matching (DEM) circuit includes: a plurality of bipolar junction transistors (BJTs), each of the plurality of BJTs having a base terminal and a collector terminal coupled to electrical ground; a plurality of pairs of force switches, each pair of force switches coupled to an emitter of a respective one of the plurality of BJTs; a plurality of pairs of sense switches, where each pair of sense switches is coupled to the emitter of a respective one of the plurality of BJTs, a first switch in each pair of sense switches is coupled to a first node, and a second switch in each pair of sense switches is coupled to a second node; a first current source coupled to a first switch in each pair of force switches; and a second current source coupled to a second switch in each pair of force switches.

Abstract: In an example implementation, an integrated circuit (IC) includes: a plurality of transistors disposed in a plurality of locations on a die of the IC; conductors coupled to terminals of each of the plurality of transistors; a digital-to-analog converter (DAC), coupled to the conductors, to drive voltage signals to the plurality of transistors in response to a digital input; and an analog-to-digital converter (ADC), coupled to at least a portion of the conductors, to generate samples in response to current signals induced in the plurality of transistors in response to the voltage signals, the samples being indicative of at least one electrostatic characteristic for the plurality of transistors.

Abstract: An example voltage reference circuit includes: a reference circuit comprising a first circuit configured to generate a proportional-to-temperature current and corresponding first control voltage and a second circuit configured to generate a complementary-to-temperature current and corresponding second control voltage; a first current source coupled to a first load circuit, the first current source generating a sum current of the proportional-to-temperature current and the complementary-to-temperature current in response to the first and second control voltages, the first load circuit generating a zero temperature coefficient (Tempco) voltage from the sum current; and a second current source coupled to a second load circuit, the second current source generating the sum current of the proportional-to-temperature current and the complementary-to-temperature current in response to the first and second control voltages, the second load circuit generating a negative Tempco voltage from the sum current and the compl

Abstract: Methods and apparatus are described for detecting both single event latch-up (SEL) and electrical overvoltage stress (EOS) using a single, reconfigurable detection circuit. One example circuit capable of detecting a latch-up state and an overvoltage condition generally includes an impedance element coupled to a power supply node; a voltage divider coupled to the power supply node; a multiplexer having a first input coupled to a tap of the voltage divider, a second input coupled to a first portion of the impedance element, and a third input coupled to a second portion of the impedance element; a reference generator; and an analog-to-digital converter (ADC) having a first input coupled to an output of the multiplexer and a second input coupled to an output of the reference generator.

Abstract: An example voltage reference circuit includes: a reference circuit comprising a first circuit configured to generate a proportional-to-temperature current and corresponding first control voltage and a second circuit configured to generate a complementary-to-temperature current and corresponding second control voltage; a first current source coupled to a first load circuit, the first current source generating a sum current of the proportional-to-temperature current and the complementary-to-temperature current in response to the first and second control voltages, the first load circuit generating a zero temperature coefficient (Tempco) voltage from the sum current; and a second current source coupled to a second load circuit, the second current source generating the sum current of the proportional-to-temperature current and the complementary-to-temperature current in response to the first and second control voltages, the second load circuit generating a negative Tempco voltage from the sum current and the compl

Abstract: A device may include a voltage-to-current converter circuit having an operational transconductance amplifier (OTA), the voltage-to-current converter circuit for generating a bias current that is proportional to a reference voltage at a reference voltage input port of the OTA, and a bias current feedback path for providing the bias current to a bias current input port of the OTA. The device may further include a startup current generator circuit coupled to the bias current input port of the OTA, the startup current generator circuit controllable to provide a startup current to the bias current input port during a startup of the device and to be deactivated after the startup of the device.

Abstract: In an example, an apparatus includes an analog switch having an n-type metal oxide semiconductor (NMOS) circuit in parallel with a p-type metal oxide semiconductor (PMOS) circuit between a switch input and a switch output. The analog switch is responsive to an enable signal that determines switch state thereof. The NMOS circuit includes a switch N-channel transistor coupled to a buffer N-channel transistor, a gate of the switch N-channel transistor coupled to the enable signal and a gate of the buffer N-channel transistor coupled to a modulated N-channel gate voltage. The PMOS circuit including a switch P-channel transistor coupled to a buffer P-channel transistor, a gate of the switch P-channel transistor coupled to a complement of the enable signal and a gate of the buffer P-channel transistor coupled to a modulated P-channel gate voltage.

Abstract: A circuit for implementing a multifunction output generator is described. The circuit comprises an amplifier circuit having a first input and a second input; a voltage generator coupled at a first node to a first input of the amplifier circuit; a controllable current source configured to provide a variable current to the first node; and a switching circuit enabling the operation of the amplifier circuit in a first mode for sensing a temperature and a second mode for providing a reference voltage. A method of implementing a multifunction output generator is described.

Abstract: An example dynamic element matching (DEM) circuit includes: a plurality of bipolar junction transistors (BJTs), each of the plurality of BJTs having a base terminal and a collector terminal coupled to electrical ground; a plurality of pairs of force switches, each pair of force switches coupled to an emitter of a respective one of the plurality of BJTs; a plurality of pairs of sense switches, where each pair of sense switches is coupled to the emitter of a respective one of the plurality of BJTs, a first switch in each pair of sense switches is coupled to a first node, and a second switch in each pair of sense switches is coupled to a second node; a first current source coupled to a first switch in each pair of force switches; and a second current source coupled to a second switch in each pair of force switches.