Abstract: A technique relates to a superconducting airbridge on a structure. A first ground plane, resonator, and second ground plane are formed on a substrate. A first lift-off pattern is formed of a first lift-off resist and a first photoresist. The first photoresist is deposited on the first lift-off resist. A superconducting sacrificial layer is deposited while using the first lift-off pattern. The first lift-off pattern is removed. A cross-over lift-off pattern is formed of a second lift-off resist and a second photoresist. The second photoresist is deposited on the second lift-off resist. A cross-over superconducting material is deposited to be formed as the superconducting airbridge while using the cross-over lift-off pattern. The cross-over lift-off pattern is removed. The superconducting airbridge is formed to connect the first and second ground planes by removing the superconducting sacrificial layer underneath the cross-over superconducting material. The superconducting airbridge crosses over the resonator.

Abstract: Semiconductor devices and electronics packaging methods include integrated circuit chips having redundant signal bond pads along with signal bond pads connected to the same signal port for non-destructive testing of the integrated circuit chips prior to packaging. Electrical testing is made via the redundant signal bond after which qualified integrated circuit chips can be attached to a pristine and bumped final interposer or printed circuit board to provide increased reliability to the assembled electronic package.

Abstract: Semiconductor devices and electronics packaging methods include integrated circuit chips having redundant signal bond pads along with signal bond pads connected to the same signal port for non-destructive testing of the integrated circuit chips prior to packaging. Electrical testing is made via the redundant signal bond after which qualified integrated circuit chips can be attached to a pristine and bumped final interposer or printed circuit board to provide increased reliability to the assembled electronic package.

Abstract: A technique relates to a superconducting airbridge on a structure. A first ground plane, resonator, and second ground plane are formed on a substrate. A first lift-off pattern is formed of a first lift-off resist and a first photoresist. The first photoresist is deposited on the first lift-off resist. A superconducting sacrificial layer is deposited while using the first lift-off pattern. The first lift-off pattern is removed. A cross-over lift-off pattern is formed of a second lift-off resist and a second photoresist. The second photoresist is deposited on the second lift-off resist. A cross-over superconducting material is deposited to be formed as the superconducting airbridge while using the cross-over lift-off pattern. The cross-over lift-off pattern is removed. The superconducting airbridge is formed to connect the first and second ground planes by removing the superconducting sacrificial layer underneath the cross-over superconducting material. The superconducting airbridge crosses over the resonator.

Abstract: A semiconductor structure and methods of forming the semiconductor structure generally includes providing a thermocompression bonded superconducting metal layer sandwiched between a first silicon substrate and a second silicon substrate. The second substrate includes a plurality of through silicon vias to the thermocompression bonded superconducting metal layer. A second superconducting metal is electroplated into the through silicon vias using the thermocompression bonded superconducting metal layer as a bottom electrode during the electroplating process, wherein the filling is from the bottom upwards.

Abstract: A semiconductor structure and methods of forming the semiconductor structure generally includes providing a thermocompression bonded superconducting metal layer sandwiched between a first silicon substrate and a second silicon substrate. The second substrate includes a plurality of through silicon vias to the thermocompression bonded superconducting metal layer. A second superconducting metal is electroplated into the through silicon vias using the thermocompression bonded superconducting metal layer as a bottom electrode during the electroplating process, wherein the filling is from the bottom upwards.

Abstract: A semiconductor structure and methods of forming the semiconductor structure include a solder bump self-aligned to a through-substrate-via, wherein the solder bump and the through-substrate-via are formed of a conductive metal material, and wherein the through-substrate-via is coupled to a buried metallization layer, which is formed of a different conductive metal material.

Abstract: A semiconductor structure and methods of forming the semiconductor structure include a solder bump self-aligned to a through-substrate-via, wherein the solder bump and the through-substrate-via are formed of a conductive metal material, and wherein the through-substrate-via is coupled to a buried metallization layer, which is formed of a different conductive metal material.

Abstract: A MEMS device comprises an electro mechanical element in a sealed chamber containing a gas comprising a reactive gas selected to react with any contaminants that may be present or formed on the operating surfaces of the device in a manner to maximize the electrical conductivity of the surfaces during operation of the device. The MEMS device may comprise a MEMS switch having electrical contacts as the operating surfaces. The reactive gas may comprise hydrogen or an azane, optionally mixed with an inert gas, or any combination of the gases. The corresponding process provides a means to substantially reduce or eliminate contaminants present or formed on the operating surfaces of MEMS devices in a manner to maximize the electrical conductivity of the surfaces during operation of the devices.

Abstract: Embodiments are directed to a method of forming a conductive via. The method includes forming an opening in a substrate and forming a conductive material along sidewall regions of the opening, wherein the conductive material occupies a first portion of an area within the opening. The method further includes forming an insulating fill in a second portion of the area within the opening, wherein at least one surface of the conductive material and at least one surface of the insulating fill are substantially coplanar with a front surface of the substrate.

Abstract: Embodiments are directed to a method of forming a conductive via. The method includes forming an opening in a substrate and forming a conductive material along sidewall regions of the opening, wherein the conductive material occupies a first portion of an area within the opening. The method further includes forming a conductive fill in a second portion of the area within the opening, wherein at least one surface of the conductive material and at least one surface of the conductive fill are substantially coplanar with a front surface of the substrate.

Abstract: Embodiments are directed to a coupler system including a semiconductor wafer, an interconnect layer formed over the semiconductor wafer and a connector that is physically secured and electronically coupled to the interconnect layer. In one or more embodiments, the connector is physically secured and electronically coupled to the interconnect layer by a structure comprising an bond layer and an electrically conductive layer. In one or more embodiments, the structure is formed according to a methodology that includes forming a bond layer over the interconnect layer, forming the electrically conductive layer as a solder layer over the bond layer, and applying a reflow operation to at least the solder layer.

Abstract: A MEMS device comprises an electro mechanical element in a sealed chamber containing a gas comprising a reactive gas selected to react with any contaminants that may be present or formed on the operating surfaces of the device in a manner to maximize the electrical conductivity of the surfaces during operation of the device. The MEMS device may comprise a MEMS switch having electrical contacts as the operating surfaces. The reactive gas may comprise hydrogen or an azane, optionally mixed with an inert gas, or any combination of the gases. The corresponding process provides a means to substantially reduce or eliminate contaminants present or formed on the operating surfaces of MEMS devices in a manner to maximize the electrical conductivity of the surfaces during operation of the devices.

Abstract: A technique relates to a superconducting airbridge on a structure. A first ground plane, resonator, and second ground plane are formed on a substrate. A first lift-off pattern is formed of a first lift-off resist and a first photoresist. The first photoresist is deposited on the first lift-off resist. A superconducting sacrificial layer is deposited while using the first lift-off pattern. The first lift-off pattern is removed. A cross-over lift-off pattern is formed of a second lift-off resist and a second photoresist. The second photoresist is deposited on the second lift-off resist. A cross-over superconducting material is deposited to be formed as the superconducting airbridge while using the cross-over lift-off pattern. The cross-over lift-off pattern is removed. The superconducting airbridge is formed to connect the first and second ground planes by removing the superconducting sacrificial layer underneath the cross-over superconducting material. The superconducting airbridge crosses over the resonator.

Abstract: A technique relates to a superconducting airbridge on a structure. A first ground plane, resonator, and second ground plane are formed on a substrate. A first lift-off pattern is formed of a first lift-off resist and a first photoresist. The first photoresist is deposited on the first lift-off resist. A superconducting sacrificial layer is deposited while using the first lift-off pattern. The first lift-off pattern is removed. A cross-over lift-off pattern is formed of a second lift-off resist and a second photoresist. The second photoresist is deposited on the second lift-off resist. A cross-over superconducting material is deposited to be formed as the superconducting airbridge while using the cross-over lift-off pattern. The cross-over lift-off pattern is removed. The superconducting airbridge is formed to connect the first and second ground planes by removing the superconducting sacrificial layer underneath the cross-over superconducting material. The superconducting airbridge crosses over the resonator.

Abstract: A technique relates to a superconducting airbridge on a structure. A first ground plane, resonator, and second ground plane are formed on a substrate. A first lift-off pattern is formed of a first lift-off resist and a first photoresist. The first photoresist is deposited on the first lift-off resist. A superconducting sacrificial layer is deposited while using the first lift-off pattern. The first lift-off pattern is removed. A cross-over lift-off pattern is formed of a second lift-off resist and a second photoresist. The second photoresist is deposited on the second lift-off resist. A cross-over superconducting material is deposited to be formed as the superconducting airbridge while using the cross-over lift-off pattern. The cross-over lift-off pattern is removed. The superconducting airbridge is formed to connect the first and second ground planes by removing the superconducting sacrificial layer underneath the cross-over superconducting material. The superconducting airbridge crosses over the resonator.

Abstract: Apparatus and methods are provided for high density packaging of semiconductor chips using silicon space transformer chip level package structures, which allow high density chip interconnection and/or integration of multiple chips or chip stacks high I/O interconnection and heterogeneous chip or function integration.

Abstract: A method for formation of a segregated interfacial dopant layer at a junction between a semiconductor material and a silicide layer includes depositing a doped metal layer over the semiconductor material; annealing the doped metal layer and the semiconductor material, wherein the anneal causes a portion of the doped metal layer and a portion of the semiconductor material to react to form the silicide layer on the semiconductor material, and wherein the anneal further causes the segregated interfacial dopant layer to form between the semiconductor material and the silicide layer, the segregated interfacial dopant layer comprising dopants from the doped metal layer; and removing an unreacted portion of the doped metal layer from the silicide layer.

Abstract: Disclosed are a method and a system for processing a semiconductor structure of the type including a substrate, a dielectric layer, and a TaN—Ta liner on the dielectric layer. The method comprises the step of using XeF2 to remove at least a portion of the TaN—Ta liner completely to the dielectric layer. In the preferred embodiments, the present invention uses XeF2 selective gas phase etching as alternatives to Ta—TaN Chemical Mechanical Polishing (CMP) as a basic “liner removal process” and as a “selective cap plating base removal process.” In this first use, XeF2 is used to remove the metal liner, TaN—Ta, after copper CMP. In the second use, the XeF2 etch is used to selectively remove a plating base (TaN—Ta) that was used to form a metal cap layer over the copper conductor.

Abstract: A surface cleaning apparatus comprising a chamber, and a thermal transfer device. The chamber is capable of holding a semiconductor structure therein. The thermal transfer device is connected to the chamber. The thermal transfer device has a surface disposed inside the chamber for contacting the semiconducting structure and controlling a temperature of the semiconductor structure in contact with the surface. The thermal transfer device has a thermal control module connected to the surface for heating and cooling the surface to thermally cycle the surface. The thermal control module effects a substantially immediate thermal response of the surface when thermally recycling the surface.