Abstract: The present invention relates to a multiplication logic for signed multiplication of two numbers to obtain a double precision product in two's complement notation, each quantity being in serial form with the least significant bit first. The multiplier may be in either two's complement, sign magnitude, or unsigned notation, and the multiplicand in two's complement notation. With adjustment of a timing waveform, the multiplication logic will accommodate multiplicands of any word length and also various multiplier word lengths below a design maximum. With shorter multipliers, separate provisions are made for entry of the sign. The logic contains integrated timing responsive to the externally supplied timing waveform, a measure which simplifies application as operands are varied. The multiplication logic is suitable for use in a large number of digital applications including digital filters, correlation, convolution, squaring and polynomial evaluation.

Abstract: The invention relates to an arithmetic unit fabricated by large scale integration techniques and to an improved digital network of increased accuracy in which the unit finds application. The integrated circuit comprises an initial summing means, rounding means, full precision multiplication logic and three successive summing means, all elements being successively connected, and all except the first having both internal and external input terminals. The unit is flexible in respect to the length of the operands and their sign notation. The terminals are readily cascaded, permitting interconnection of the unit with like integrated circuit units and with external delay elements. The invention is applicable in a variety of complex operations including digital filtering, correlation, convolution, polynomial evaluation and squaring. In many of these applications, mixed precision and rounding provide increased accuracy in the resulting digital networks.

Abstract: The invention relates to an integrated arithmetic unit for computing summed indexed products and suitable for fabrication by large scale integration techniques. The arithmetic unit comprises a vector adder and a vector multiplier. The vector adder includes a pair of serially connected summers each with one sign controlled input. The vector multiplier comprises two single precision multiplication logics whose outputs are each provided with a sign control. The appropriately signed outputs of the two multiplication logics are then summed to provide the output of the arithmetic unit. The input data are introduced and the processed output data, both of which may be complex, are derived from the unit in bit serial, word parallel computation when a greater speed of computation is required and used repetitively with suitable multiplexing provisions when a lesser speed of computation is required. A major application of the arithmetic units is in the computation of multiple point Fast Fourier Transforms (FFT).

Abstract: The present invention relates to signed multiplication logic for multiplying two serial binary numbers to obtain a serial binary product, the multiplicand containing magnitude and sign information in two's complement notation, the multiplier containing magnitude information, and the product containing magnitude and sign information in two's complement notation, all three bit streams occurring serially at equal word rates with the least significant bit first in time. The logic is composed of a plurality of largely identical multiplication cells which form partial products which are summed in largely identical summation cells to form the final product. Each multiplication cell stores a multiplier bit, contains a stage of a multiplicand shift register and a stage of a timing waveform shift register. Means are provided for truncation of the multiplicand and product rounding under timing waveform control. The logic is flexible and may be used to form single or double precision products.