Abstract: An input protection circuit (200) and associated method are disclosed for protecting a circuit input (VINP) from positive and negative overvoltages at an input voltage (VIN) with a high-voltage PMOSFET (P1) having a gate, a drain connected across a zener diode (ZD1) to the gate, and a source connected to receive an input voltage; a blocking FET (N1) having a gate connected to a power supply voltage, a drain connected across a zener diode (ZD2) to the power supply voltage, and a source connected to the gate of the high-voltage PMOSFET; a high-voltage NMOSFET (N3) having a gate connected to the power supply voltage, a source providing the protected output voltage and connected across a zener diode (ZD3) to the gate, and a drain connected to a source follower node and a level shifter circuit (214) connected between the drain of the high-voltage PMOSFET and the source follower node.

Abstract: An input protection circuit (200) and associated method are disclosed for protecting a circuit input (VINP) from positive and negative overvoltages at an input voltage (VIN) with a high-voltage PMOSFET (P1) having a gate, a drain connected across a zener diode (ZD1) to the gate, and a source connected to receive an input voltage; a blocking FET (N1) having a gate connected to a power supply voltage, a drain connected across a zener diode (ZD2) to the power supply voltage, and a source connected to the gate of the high-voltage PMOSFET; a high-voltage NMOSFET (N3) having a gate connected to the power supply voltage, a source providing the protected output voltage and connected across a zener diode (ZD3) to the gate, and a drain connected to a source follower node and a level shifter circuit (214) connected between the drain of the high-voltage PMOSFET and the source follower node.

Abstract: A device for over-temperature detection having a test mode is presented. The device includes a temperature detection circuit having first and second transistors. The temperature detection circuit is configured so that when an ambient temperature of the temperature detection circuit is less than a temperature threshold, a voltage at an emitter terminal of the second transistor is less than a voltage at an emitter terminal of the first transistor minus VT*ln(N), and when the ambient temperature of the temperature detection circuit is greater than the temperature threshold, the voltage at the emitter terminal of the second transistor is greater than a voltage at the emitter terminal of the first transistor minus VT*ln(N). The device includes a measurement circuit configured to generate an output voltage that is proportional to a difference between the temperature threshold of the temperature detection circuit and the ambient temperature of the temperature detection circuit.

Abstract: An integrated circuitry includes a first logic block coupled between a first power supply terminal and a second power supply terminal. The first logic block includes a first scan chain and a configurable defect coupled to a scan output node of the first scan chain. The configurable defect has a logic node and a conductive element coupled between the logic node and the first or the second power supply terminal. The configurable defect is configured to, during a quiescent current testing mode, place a predetermined logic state on the logic node such that a current flows through the conductive element. The current can be detected by external equipment.

Abstract: A device for over-temperature detection having a test mode is presented. The device includes a temperature detection circuit having first and second transistors. The temperature detection circuit is configured so that when an ambient temperature of the temperature detection circuit is less than a temperature threshold, a voltage at an emitter terminal of the second transistor is less than a voltage at an emitter terminal of the first transistor minus VT*ln(N), and when the ambient temperature of the temperature detection circuit is greater than the temperature threshold, the voltage at the emitter terminal of the second transistor is greater than a voltage at the emitter terminal of the first transistor minus VT*ln(N). The device includes a measurement circuit configured to generate an output voltage that is proportional to a difference between the temperature threshold of the temperature detection circuit and the ambient temperature of the temperature detection circuit.

Abstract: A reference circuit includes a bandgap core circuit and a cascode amplifier. The bandgap core circuit includes a first bipolar junction transistor (BJT), a second BJT having a control electrode coupled to a control electrode of the first BJT, a first resistor coupled to the first BJT and the second BJT, and a second resistor coupled to the second BJT. The cascode amplifier circuit includes a first branch coupled to the first BJT and a second branch coupled to the second resistor.

Abstract: A reference circuit includes a bandgap core circuit and a cascode amplifier. The bandgap core circuit includes a first bipolar junction transistor (BJT), a second BJT having a control electrode coupled to a control electrode of the first BJT, a first resistor coupled to the first BJT and the second BJT, and a second resistor coupled to the second BJT. The cascode amplifier circuit includes a first branch coupled to the first BJT and a second branch coupled to the second resistor.

Abstract: A device for over-temperature detection having a test mode is presented. The device includes a temperature detection circuit having first and second transistors. The temperature detection circuit is configured so that when an ambient temperature of the temperature detection circuit is less than a temperature threshold, a voltage at an emitter terminal of the second transistor is less than a voltage at an emitter terminal of the first transistor minus VT*In(N), and when the ambient temperature of the temperature detection circuit is greater than the temperature threshold, the voltage at the emitter terminal of the second transistor is greater than a voltage at the emitter terminal of the first transistor minus VT*In(N). The device includes a measurement circuit configured to generate an output voltage that is proportional to a difference between the temperature threshold of the temperature detection circuit and the ambient temperature of the temperature detection circuit.

Abstract: An integrated circuitry includes a first logic block coupled between a first power supply terminal and a second power supply terminal. The first logic block includes a first scan chain and a configurable defect coupled to a scan output node of the first scan chain. The configurable defect has a logic node and a conductive element coupled between the logic node and the first or the second power supply terminal. The configurable defect is configured to, during a quiescent current testing mode, place a predetermined logic state on the logic node such that a current flows through the conductive element. The current can be detected by external equipment.

Abstract: A voltage supply regulator includes a first output resistor including a first terminal coupled to an output voltage of the voltage supply regulator and a second terminal; a first comparator including a first input coupled to a reference voltage, a second input coupled to the second terminal of the first output resistor, and an output coupled to a base of a first regulator transistor; a current mirror coupled to a collector of the first regulator transistor; and an slew rate detector coupled to the current mirror that includes a first terminal coupled to control electrodes of first and second transistors in the current mirror, and a detection bipolar junction transistor having a collector coupled to the control electrodes of the first and second transistors in the current mirror, and a base coupled to a second terminal of the capacitor.

Abstract: A voltage supply regulator includes a first output resistor including a first terminal coupled to an output voltage of the voltage supply regulator and a second terminal; a first comparator including a first input coupled to a reference voltage, a second input coupled to the second terminal of the first output resistor, and an output coupled to a base of a first regulator transistor; a current mirror coupled to a collector of the first regulator transistor; and an slew rate detector coupled to the current mirror that includes a first terminal coupled to control electrodes of first and second transistors in the current mirror, and a detection bipolar junction transistor having a collector coupled to the control electrodes of the first and second transistors in the current mirror, and a base coupled to a second terminal of the capacitor.

Abstract: An integrated circuit (IC) having a heat-generating element, such as a power MOSFET, a current-carrying conductor coupled to the heat-generating element, a sense conductor adjacent the current-carrying conductor, and a failure-detection circuit coupled to the sense conductor. When thermal cycling of the IC causes the resistance of the sense conductor to become greater than a temperature-dependent threshold value, the failure-detection circuit generates a signal indicating that the integrated circuit will soon fail. The resistance of the sense conductor is determined by injecting a current into the sense conductor to generate a voltage. The temperature-dependent threshold value is a voltage generated by injecting a current into a reference conductor disposed away from the current-carrying and sense conductors. A voltage comparator compares the two voltages to generate the output.

Abstract: A wireless charging system includes a power transmitting device and a power receiving device. In the transmitting device, a transmitting coil converts a drive signal from a drive signal circuit into an alternating magnetic field. In the receiving device, a receiving coil produces an alternating waveform from the magnetic field, and a rectifier rectifies the alternating waveform to deliver power having a rectified voltage. A modulation circuit causes a loading circuit to be coupled to and uncoupled from the receiving coil at a pre-determined modulation rate when, for example, the rectified voltage is greater than a threshold voltage. Back in the transmitting device, a modulation detector circuit detects modulation of the load impedance, and when the load impedance is modulating at the pre-determined modulation rate, causes the drive signal circuit to adjust a characteristic of the drive signal, resulting in an adjustment in an intensity of the magnetic field.

Abstract: Operation of an insulated gate bipolar transistor (IGBT) is monitored by an apparatus that has a capacitor connected between a collector of the IGBT and an input node. A processing circuit, coupled to the input node, responds to current flowing through the capacitor by providing an indication whether a voltage level at the collector is changing and the rate of that change. The processing circuit also employs the capacitor current to provide an output voltage that indicates the voltage at the IGBT collector.

Abstract: A buffer or voltage protection circuit, a circuit including same, and an associated method of operation are disclosed. In one example embodiment, the integrated circuit includes a first input terminal, a first circuit portion having a second input terminal, and a second circuit portion. The second circuit portion includes a transistor device having first, second, and third ports, where the first and second ports are respectively electrically coupled to the first input terminal and second input terminal, respectively. Additionally, the second circuit portion also includes a diode-type device that is electrically coupled between the third port and either a power source or a power input terminal, and a buffer/driver circuit and a capacitor coupled in series between the third and second ports. The second circuit portion operates to prevent the second input terminal from being exposed to an undesirably-high voltage level.

Abstract: A DC-DC converter (100) includes a switching transistor (M0) connecting an input power terminal (VIN) to an inductor (114) that is also connected to an output power terminal (VOUT), a synchronous rectification transistor (M1) connected to a junction node (113) between the inductor (114) and the switching transistor (M0), and a synchronous rectifier control circuit (200) with an integration capacitor (226) having a voltage that is charged and discharged by first and second current sources (210, 220) to track the charging and discharging of the inductor current, thereby generating a synchronous rectifier control signal (SR) that is applied to the synchronous rectification transistor to discharge the inductor current to zero.

Abstract: The embodiments described herein provide antifuse devices and methods that can be utilized in a wide variety of semiconductor devices. In one embodiment a semiconductor device is provided that includes an antifuse, a first diode coupled with the antifuse in a parallel combination, and a second diode coupled in series with the parallel combination. In such an embodiment the first diode effectively provides a bypass current path that can reduce the voltage across the antifuse when other antifuses are being programmed. As such, these embodiments can provide improved ability to tolerate programming voltages without damage or impairment of reliability.

Abstract: A proportional-to-absolute-temperature (“PTAT”) circuit includes a bias component; first, second, third, and fourth transistors; an output transistor; and a first resistive component. A first terminal of the bias component is coupled to a voltage supply node. The first and second transistors are connected to a second terminal of the bias component. The third and fourth transistors have different current densities. The first transistor is coupled to the third transistor. The second transistor is coupled to the fourth transistor. The fourth transistor and the first resistive component are coupled to a voltage common node. The output transistor has a control terminal coupled to the second and fourth transistors, a first current terminal connected to an output node, and a second current terminal coupled to the third transistor and the first resistive component. The PTAT circuit is configured to generate at least a portion of a PTAT current at the output node.

Abstract: Embodiments of inductive communication devices include first and second galvanically isolated IC die and a dielectric structure. Each IC die has a coil proximate to a first surface of the IC die. The IC die are arranged so that the first surfaces of the IC die face each other, and the first coil and the second coil are aligned across a gap between the first and second IC die. The dielectric structure is positioned within the gap directly between the first and second coils, and a plurality of conductive structures are positioned in or on the dielectric structure and electrically coupled with the second IC die. The conductive structures include portions configured to function as bond pads, and the bond pads may be coupled to package leads using wirebonds. During operation, signals are conveyed between the IC die through inductive coupling between the coils.

Abstract: An integrated circuit (IC) having a heat-generating element, such as a power MOSFET, a current-carrying conductor coupled to the heat-generating element, a sense conductor adjacent the current-carrying conductor, and a failure-detection circuit coupled to the sense conductor. When thermal cycling of the IC causes the resistance of the sense conductor to become greater than a temperature-dependent threshold value, the failure-detection circuit generates a signal indicating that the integrated circuit will soon fail. The resistance of the sense conductor is determined by injecting a current into the sense conductor to generate a voltage. The temperature-dependent threshold value is a voltage generated by injecting a current into a reference conductor disposed away from the current-carrying and sense conductors. A voltage comparator compares the two voltages to generate the output.