Patents by Inventor John Melanson

John Melanson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070075884
    Abstract: A system and method calibrate a redundant number system analog-to-digital converter (RNS ADC) using successive approximations of multiple input signals and approximating each input signal at least twice. The RNS ADC includes N analog converter reference elements, each of the analog converter reference elements is associated with a weight in a weight vector W, and N is an integer greater than one. The system and method successively approximate each of M distinct analog input signals twice to generate M respective pairs of successive approximation converter reference element vectors, C1j and C2j,that correspond to digital approximations of the input signals, wherein j ? {0, 1, . . . , M-1}, wherein M is a positive integer. The system and method utilize differences between the successive approximation converter reference element vectors, C1j and C2j to determine a final weight vector WB.
    Type: Application
    Filed: October 2, 2006
    Publication date: April 5, 2007
    Inventors: John Melanson, Clinton Wolff
  • Publication number: 20070018866
    Abstract: A digital signal processing system includes a delta sigma modulator that maintains a low pass output during quantizer overload prevention conditions. In at least one embodiment, the delta sigma modulator includes a quantizer overload protected delta sigma modulator with an N-order feedback-type loop filter. A quantizer of the delta sigma modulator provides feedback to at least the first two filter stages of the loop filter. The loop filter includes at least N successive filter stages and limits an output of an initial filter stage during quantizer overload prevention conditions. If limiting the output of the initial filter stage is insufficient to prevent quantizer overload, the delta sigma modulator can progressively limit an output of at least the next successive filter stage to prevent quantizer overload, where N is a positive integer greater than or equal to two (2).
    Type: Application
    Filed: July 22, 2005
    Publication date: January 25, 2007
    Inventor: John Melanson
  • Publication number: 20070003075
    Abstract: A signal processing system includes a level dependent bass management system. The level dependent bass management system utilizes audio input signal level information to apply at least one of multiple, available bass management solutions to generate one or more output signals from the audio input signal. In at least one embodiment, initially the level dependent bass management system boosts components of the audio input signal in the low frequency range by an amount sufficient to at least partially compensate for low frequency attenuation of the first speaker without exceeding one or more acceptable limitations of the signal processing system. If boosting alone cannot completely compensate for low frequency attenuation of the first speaker without exceeding one or more acceptable limitations of the signal processing system, the level dependent bass management system processes the audio input signal using an alternate low frequency management solution.
    Type: Application
    Filed: September 29, 2005
    Publication date: January 4, 2007
    Inventors: Joel Cooper, John Melanson, Pu Liu
  • Patent number: 7158045
    Abstract: A method and apparatus for maintaining an ideal frequency ratio between numerically-controlled frequency sources provides a mechanism for maintaining coherence between multiple synchronization references where a known ideal rational relationship between the sources is known. Multiple numerically controlled oscillators (NCOs) generate the multiple synchronization references, which may be clock signals or numeric phase representations and the outputs of the NCOs are compared with a ratiometric frequency comparator that determines whether there is an error in the ratio between the NCO outputs. The frequency of one of the NCOs is then adjusted with a frequency correction factor provided by the ratiometric frequency comparator. The NCO inputs can represent ratios of the synchronization reference frequencies to a fixed reference clock and the NCOs clocked by the fixed reference clock.
    Type: Grant
    Filed: March 24, 2005
    Date of Patent: January 2, 2007
    Assignee: Cirrus Logic, Inc.
    Inventors: Daniel Gudmunson, John Melanson, Rahul Singh, Ahsan Chowdhury
  • Patent number: 7154562
    Abstract: A method of gamma correction includes selecting lower and upper reference curves corresponding to selected reference gamma values. A gamma correction curve is generated from a corresponding gamma correction value and cross-correlated with the upper and lower reference curves to generate a corresponding set of cross-correlation factors. The set of cross-correlation factors are stored and indexed to the corresponding gamma value. An input value is received for gamma correction with the corresponding gamma value. Data from the upper and lower reference curves indexed by the input value are then operated one with the cross-correlation factors to generate a gamma corrected output value.
    Type: Grant
    Filed: October 14, 2003
    Date of Patent: December 26, 2006
    Assignee: Cirrus Logic, Inc.
    Inventors: Ahsan Chowdhury, Anand Venkitachalam, John Melanson
  • Publication number: 20060232331
    Abstract: A chopping amplifier and method for chopping an input signal are disclosed. The chopping amplifier and method utilize at least two chopping amplifier stages. A chopping operation of an input signal is segmented across two or more chopping amplifier stages, and the two or more chopping amplifier stages are responsive to a master controller. Chop clock signals of the chopping amplifier stages are staggered so that they have non-overlapping periods and at least one of the chopping amplifier stages is not operating in an open loop at any given time. The non-overlapping periods are periodic so that a master chop clock of the master controller can be operated at a lower chop clock frequency. For every doubling of N number of chopping amplifier stages, magnitudes of chopping artifacts and aliased components are each respectively reduced by 3 dB.
    Type: Application
    Filed: June 19, 2006
    Publication date: October 19, 2006
    Inventors: Karl Thompson, John Melanson, Chung-Kai Chow, Ammisetti Prasad
  • Publication number: 20060158244
    Abstract: An operational amplifier including at least one amplifier stage and chopping circuitry for chopping an input signal to the amplifier stage and an output signal from the chopping signal having a frequency randomly varying within the selected frequency band.
    Type: Application
    Filed: January 14, 2005
    Publication date: July 20, 2006
    Applicant: Cirrus Logic, Inc.
    Inventors: Murari Kejariwal, Gowtham Vemulapalli, John Melanson
  • Publication number: 20060129256
    Abstract: A simplified digital implementation of a fourth order Linkwitz-Riley crossover network is provided using approximations and transformations of the classical form. The approximation is particularly beneficial when the crossover frequency is low relative to the digital sampling rate, such as when an audio stream is split between bass and treble at about 30-300 Hz and the sampling frequency is about 100 times the cutoff frequency or higher. Rather than merely cascading two sets of second order filters, such as Butterworth filters, a fourth order transfer function is more directly implemented. Conventional transfer functions are simplified through approximations resulting in the elimination of all except one parameter, c, which is a linear function of the cutoff frequency. Additionally, multipliers are moved in line with the integrator elements.
    Type: Application
    Filed: December 15, 2004
    Publication date: June 15, 2006
    Applicant: Cirrus Logic, Incorporated
    Inventors: John Melanson, Emmanuel Marchais
  • Publication number: 20060114031
    Abstract: A phase-locked loop circuit has a fractional-frequency-interval phase frequency detector, a charge pump, an oscillator, and a divider. The fractional-frequency-interval phase frequency detector has a phase frequency detector unit that is utilized as or comprises a plurality of phase frequency detector units. The divider is responsive to the oscillator and provides divider values for dividing an oscillator frequency by the divider values to provide a feedback frequency of a feedback loop signal of the phase-locked loop circuit. A reference input frequency is input as a first input into the phase frequency detector unit. The feedback frequency is input and selectively delayed as second inputs into the phase frequency detector unit so that the second inputs are aligned for input according to the reference input frequency and an oscillator frequency is, in effect, responsive to the phase frequency detector units and allowed to be divided by a fractional-integer divider value.
    Type: Application
    Filed: January 13, 2006
    Publication date: June 1, 2006
    Inventor: John Melanson
  • Publication number: 20060077296
    Abstract: A video decoder in which the video source clock is generated entirely in the digital domain is disclosed herein. By creating a virtual version of the source clock in a numeric oscillator, the amount of noise in the system is substantially reduced. Furthermore, by transferring the digitized video signal, sampled with an asynchronous crystal clock, into the source clock domain, the accuracy of the brightness (amplitude) and color (phase) information can be greatly enhanced.
    Type: Application
    Filed: October 13, 2004
    Publication date: April 13, 2006
    Inventors: Daniel Gudmundson, John Melanson, Rahul Singh, Ahsan Chowdhury
  • Publication number: 20060078054
    Abstract: Video decoder systems in which both the analog-to-digital converter and the composite decoder are driven by the stable sample clock, such as a crystal source. The outputs of the composite decoder are provided to a source rate converter, having an output that is provided to a digital output formatter. The digital output formatter is driven by the output clock, which may be locked to the source clock if desired. The output clock is developed by a clock generator which may be one of several different types, including a fractional N synthesizer, a direct digital synthesizer or a puncture clock.
    Type: Application
    Filed: October 13, 2004
    Publication date: April 13, 2006
    Inventors: Daniel Gudmundson, John Melanson, Rahul Singh, James Antone, Ahsan Chowdhury, Krishnan Subramoniam
  • Publication number: 20060062398
    Abstract: A downsampled adaptive filter is used to find the impulse response of a home theater system. Downsampling yields higher maximum measurable distance for given filter length. By using a Least-Mean-Square (LMS) adaptive filter, almost anything can be used as the source noise. While downsampling may decrease the resolution of the distance measurement, Adaptive Filtering allows a much broader range of test signals, as opposed to MLS (Maximum Length Sequence) in which the test signal defines the technique (a pseudo-random Maximum Length Sequence.
    Type: Application
    Filed: January 21, 2005
    Publication date: March 23, 2006
    Inventors: Joel McKee Cooper, John Melanson, Gert Rosenboom
  • Patent number: 7015853
    Abstract: Methods and apparatus are provided for reducing nonlinearities in an analog-to-digital signal converter. An analog pseudo-random noise sample is added to an analog input sample and the combined sample is converted into a digital representation. A pseudo-random digital sample corresponding to the analog noise sample is subtracted from the converted digital representation. Preferably, multiple analog noise samples are added to the analog input sample, converted and corresponding digital noise samples subtracted from the converted digital representation. The multiple digital representations are then averaged, thereby nullifying differential nonlinearities in various portions of the transfer characteristics curve of the signal converter and reducing the effects of the DNL.
    Type: Grant
    Filed: March 9, 2005
    Date of Patent: March 21, 2006
    Assignee: Cirrus Logic, Inc.
    Inventors: Clinton R. Wolff, John Melanson
  • Publication number: 20060012500
    Abstract: Look-ahead delta sigma modulators of the signal processing systems described herein can anticipate quantizer overload. By anticipating quantizer overload, the look-ahead delta sigma modulators can select an output value y(n) that may have a lower SNR but will prevent quantizer overload in the future. A quantizer overload protection process determines the amount of look-ahead depth to drive state variables of a loop filter of the look-ahead delta sigma modulator to values that would prevent future quantizer overload. By substituting a quantizer of the look-ahead delta sigma modulator with a gain and determining a closed loop impulse response of a look-ahead delta-sigma modulator, the discrete time to achieve an absolute value maximum closed loop response magnitude of the look-ahead delta-sigma modulator has been determined to be directly related to the look-ahead depth that will prevent future quantizer overload.
    Type: Application
    Filed: March 25, 2005
    Publication date: January 19, 2006
    Inventor: John Melanson
  • Publication number: 20050169419
    Abstract: A phase-locked loop circuit has a fractional-frequency-interval phase frequency detector, a charge pump, an oscillator, and a divider. The fractional-frequency-interval phase frequency detector has a phase frequency detector unit that is utilized as or comprises a plurality of phase frequency detector units. The divider is responsive to the oscillator and provides divider values for dividing an oscillator frequency by the divider values to provide a feedback frequency of a feedback loop signal of the phase-locked loop circuit. A reference input frequency is input as a first input into the phase frequency detector unit. The feedback frequency is input and selectively delayed as second inputs into the phase frequency detector unit so that the second inputs are aligned for input according to the reference input frequency and an oscillator frequency is, in effect, responsive to the phase frequency detector units and allowed to be divided by a fractional-integer divider value.
    Type: Application
    Filed: February 2, 2004
    Publication date: August 4, 2005
    Inventor: John Melanson
  • Publication number: 20050162286
    Abstract: Look-ahead delta sigma modulators of a signal processing system can selectively bias one or more output candidate vectors to alter the probability of selecting a biased output candidate vector(s) for determination of a quantization output value. The probability, within a range of error, of certain output candidate vectors being selected by a quantizer of the look-ahead delta sigma modulator can be determined. The output candidate vectors determine the quantization output values. Thus, altering the probability of selecting a certain output candidate(s) alters the probability of occurrence of a certain quantization output value(s). Detection of the altered probability allows an output signal to be identified. Identifying an output signal allows for many interesting operations including identifying a specific signal processing system source of the output signal and modifying processing of the output signal. Additionally, some quantization output values can be compressed more densely than others.
    Type: Application
    Filed: January 26, 2005
    Publication date: July 28, 2005
    Inventor: John Melanson
  • Publication number: 20050162285
    Abstract: A look-ahead delta sigma modulator utilizes pruning techniques to reduce the number of possible output candidate vectors used to determine quantization output values. The look-ahead delta-sigma modulators can also combine the pruning techniques with a reduction in the amount of processing by simplifying the computations used to generate quantizer output values. In one embodiment, the pruning techniques exploit application of superposition techniques to a loop filter response of the look-ahead delta sigma modulator. The set of possible pattern response vectors can be pruned to form a subset of P candidate pattern response vectors. If an element value of a pattern response vector proximally matches a value of the corresponding reference element of the natural response vector, a quantizer uses the proximally matching pattern response vector to determine a quantization output value.
    Type: Application
    Filed: January 26, 2005
    Publication date: July 28, 2005
    Inventor: John Melanson
  • Publication number: 20050156770
    Abstract: A signal processing system includes a jointly non-linear delta sigma modulator. In one embodiment, the jointly non-linear delta sigma modulator includes a non-linear quantization transfer function, and the output of the delta sigma modulator is defined, at least in part, by a non-linear interrelationship of multiple noise-shaping filter state variables. A look-ahead delta-sigma modulator can be implemented as a noise shaping filter and a function generator. State variables of the noise shaping filter provide the input data from which the function generator determines a quantizer output signal. Latter state variables are more dominant in determining the quantizer output signal. Accordingly, earlier state variables can be approximated to a greater degree than latter state variables without significant compromise in quantization accuracy.
    Type: Application
    Filed: January 13, 2005
    Publication date: July 21, 2005
    Inventor: John Melanson
  • Publication number: 20050156772
    Abstract: A signal processing system includes a look-ahead delta sigma modulator having an approximation generator to approximate quantizer input signals. A look-ahead delta-sigma modulator can be implemented as a noise shaping filter and a quantizer. The quantizer can be implemented as a function generator. State variables of the noise shaping filter provide the input data from which the function generator determines a quantizer output signal. Latter state variables are more dominant in determining the quantizer output signal. Accordingly, earlier state variables can be approximated to a greater degree than earlier state variables. The approximations can result in slightly lower output signal accuracy but can significantly decrease implementation cost. Additionally, latter state variables can completely dominate (i.e., be deterministic) the quantizer output signal. This situation can result in a further, slight increase in the non-linearity of one or more quantization region boundaries.
    Type: Application
    Filed: January 18, 2005
    Publication date: July 21, 2005
    Inventor: John Melanson
  • Publication number: 20050156771
    Abstract: A delta sigma modulator look-ahead IIR filter response can be divided into a natural response and a pattern response using superposition techniques. The look-ahead delta sigma modulators of the signal processing systems described herein include an infinite impulse response filter (“IIR”) that produces multiple output look-ahead natural responses to input signals having a look-ahead depth of “M”. The multiple output lookahead IIR filter reduces the amount of processing and memory used by the delta sigma modulator to generate quantizer output values. The multiple output lookahead IIR filter uses extended delay stages and modified feedback coefficients to concurrently produce multiple look-ahead natural responses. In one embodiment, the multiple output lookahead IIR filter concurrently produces M look-ahead natural responses.
    Type: Application
    Filed: January 18, 2005
    Publication date: July 21, 2005
    Inventor: John Melanson