Patents by Inventor John P. Fishburn

John P. Fishburn has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6873187
    Abstract: An electronic circuit includes delay selection units each associated with a flip-flop or other circuit element. The delay selection unit for a given one of the circuit elements is coupled between a source of a clock or other signal and a corresponding input of the circuit element, and is controllable to provide one of a number of selectable delays for the signal. One or more of the delay selection units are controlled so as to select a particular one of the selectable delays for each of the units. In an illustrative embodiment, the particular delays may be determined at least in part based on the solution of an integer nonlinear program in which the plurality of delays for a given one of the delay selection units are arranged substantially in a monotonically increasing manner and each of at least a subset of the selectable delays for the given one of the delay selection units is specified by upper and lower bounds on the corresponding delay.
    Type: Grant
    Filed: March 27, 2003
    Date of Patent: March 29, 2005
    Assignee: Lattice Semiconductor Corporation
    Inventors: William Andrews, Barry Britton, Xiaotao Chen, John P. Fishburn, Harold Scholz
  • Patent number: 6486705
    Abstract: Fractional cycle stealing units are introduced in the routing of a programmable device such as an FPGA or FPSC to increase system performance resulting from the particular clock routing. The disclosed fractional cycle stealing units enable given amounts of clock skew between individual distribution sinks, and/or between logic paths that are in series. Each of the delay elements ‘steals’ a portion of a clock cycle (and perhaps one or more full clock cycles) from subsequent circuits to provide a more reliable logical function, and to avoid the need for overall additional clock cycles. These fractional cycle stealing elements offer a signal skew adjustment at the sinks of the distribution with no additional routing congestion expense. The disclosed cycle stealing delay elements are programmable, and enable clock skew between individual distribution sinks.
    Type: Grant
    Filed: May 25, 2001
    Date of Patent: November 26, 2002
    Assignee: Lattice Semiconductor Corporation
    Inventors: William B. Andrews, Alfred E. Dunlop, John P. Fishburn, Harold N. Scholz
  • Publication number: 20020003445
    Abstract: Fractional cycle stealing units are introduced in the routing of a programmable device such as an FPGA or FPSC to increase system performance resulting from the particular clock routing. The disclosed fractional cycle stealing units enable given amounts of clock skew between individual distribution sinks, and/or between logic paths that are in series. Each of the delay elements ‘steals’ a portion of a clock cycle (and perhaps one or more full clock cycles) from subsequent circuits to provide a more reliable logical function, and to avoid the need for overall additional clock cycles. These fractional cycle stealing elements offer a signal skew adjustment at the sinks of the distribution with no additional routing congestion expense. The disclosed cycle stealing delay elements are programmable, and enable clock skew between individual distribution sinks.
    Type: Application
    Filed: May 25, 2001
    Publication date: January 10, 2002
    Inventors: William B. Andrews, Alfred E. Dunlop, John P. Fishburn, Harold N. Scholz
  • Patent number: 5633807
    Abstract: A system and method integrate mask layout tools to automate the generation of mask layouts for fabricating an integrated circuit corresponding to an input netlist and a timing specification. The mask layout is generated by the method including the steps of automatically sizing transistors specified in the netlist, clustering the sized transistors into cells, generating a cell library, and placing-and-routing the cells to generate the mask layout. The system includes associated memory and stored programs, including a plurality of mask layout tools; and a processor operated by an automatic mask layout generation program for sequentially applying the plurality of mask layout tools to generate the mask layout from the input data.
    Type: Grant
    Filed: May 1, 1995
    Date of Patent: May 27, 1997
    Assignee: Lucent Technologies Inc.
    Inventors: John P. Fishburn, Craig R. Kemp, Catherine A. Schevon, Todd R. Seigfried, Sanjiv Taneja, Yu-Chun Wu
  • Patent number: 4827428
    Abstract: A method and system for improving the design of an integrated circuit by iteratively analyzing the circuit and improving it with each iteration, until a preselected constraint is met. The design improvement is realized by selecting a model for the delay through each active element of the circuit that is characterized by a convex-function of the logarithm of the active element's size. Using the convex function model, with each iteration a static timing analysis of the circuit identifies the output that most grievously violates the specified constraint. With that output selected, an analysis of the path's timing structure identifies the active element in that path whose change in size would yield the largest improvement in performance. The size of that active element is adjusted accordingly and the iteration is repeated. For further improvement, the interconnection pattern of subnetworks of the circuit is evaluated and rearranged to improve performance.
    Type: Grant
    Filed: November 15, 1985
    Date of Patent: May 2, 1989
    Assignee: American Telephone and Telegraph Company, AT&T Bell Laboratories
    Inventors: Alfred E. Dunlop, John P. Fishburn