Patents by Inventor John Paul Strachan

John Paul Strachan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200334523
    Abstract: Systems and methods are provided for implementing a hardware accelerator. The hardware accelerator emulates a neural network, and includes a memristor crossbar array, and a non-linear filter. The memristor crossbar array can be programmed to calculate node values of the neural network. The nodes values can be calculated in accordance with rules to reduce an energy function associated with the neural network. The non-linear filter is coupled to the memristor crossbar array and programmed to harness noise signals that may be present in analog circuitry of the hardware accelerator. The noise signals can be harnessed such that the energy function associated with the neural network converges towards a global minimum and modifies the calculated node values. In some embodiments, the non-liner filter is implemented as a Schmidt trigger comparator.
    Type: Application
    Filed: April 17, 2019
    Publication date: October 22, 2020
    Inventors: Suhas Kumar, Thomas Van Vaerenbergh, John Paul Strachan
  • Publication number: 20200312406
    Abstract: A DPE memristor crossbar array system includes a plurality of partitioned memristor crossbar arrays. Each of the plurality of partitioned memristor crossbar arrays includes a primary memristor crossbar array and a redundant memristor crossbar array. The redundant memristor crossbar array includes values that are mathematically related to values within the primary memristor crossbar array. In addition, the plurality of partitioned memristor crossbar arrays includes a block of shared analog circuits coupled to the plurality of partitioned memristor crossbar arrays. The block of shared analog circuits is to determine a dot product value of voltage values generated by at least one partitioned memristor crossbar array of the plurality of partitioned memristor crossbar arrays.
    Type: Application
    Filed: March 26, 2019
    Publication date: October 1, 2020
    Inventors: Amit S. Sharma, John Paul Strachan, Catherine Graves, Suhas Kumar, Craig Warner, Martin Foltin
  • Publication number: 20200285779
    Abstract: Examples described herein relate to a security system consistent with the disclosure. For instance, the security system may comprise a sensor interface bridge connecting a gateway to an input/output (I/O) card, a Field Programmable Gate Array (FPGA) to scan data to detect an anomaly in the data while the data is in the sensor interface bridge, where a learning neural network accelerator Application-Specific Integrated Circuit (ASIC) is integrated with the FPGA and send the data without an anomaly to the gateway.
    Type: Application
    Filed: March 4, 2019
    Publication date: September 10, 2020
    Inventors: Martin Foltin, Aalap Tripathy, Harvey Edward White, JR., John Paul Strachan
  • Patent number: 10770140
    Abstract: The present disclosure provides a memristive array. The array includes a number of memristive devices. A memristive device is switchable between states and is to store information. The memristive array also includes a parallel reset control device coupled to the number of memristive devices in parallel. The parallel reset control device regulates a resetting operation for the number of memristive devices by regulating current flow through target memristive devices.
    Type: Grant
    Filed: January 27, 2016
    Date of Patent: September 8, 2020
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: John Paul Strachan, Brent Buchanan, Le Zheng
  • Publication number: 20200258587
    Abstract: An analog content addressable memory cell includes a high side and a low side. The high side encodes a high bound on a range of values and includes a first voltage divider formed of a first programmable resistor and a first electronically controlled variable resistor. The low side encodes a low bound on the range of values and includes a second voltage divider formed of a second programmable resistor and a second electronically controlled variable resistor.
    Type: Application
    Filed: February 13, 2019
    Publication date: August 13, 2020
    Inventors: Can Li, Catherine Graves, John Paul Strachan
  • Publication number: 20200242448
    Abstract: Staged neural networks and methods therefor are provided for solving NP hard/complete problems. In some embodiments, the methods include identifying a plurality of second NP hard/complete problems, wherein each of the second NP hard/complete problems is similar to the first NP hard/complete problem; identifying solutions to the second NP hard/complete problems; training a deep neural network with the second NP hard/complete problems and the solutions; providing the first NP hard/complete problem to the trained deep neural network, wherein the trained deep neural network generates a preliminary solution to the first NP hard/complete problem; and providing the preliminary solution to a recursive neural network configured to execute an energy minimization search, wherein the recursive neural network generates a final solution to the problem based on the preliminary solution.
    Type: Application
    Filed: January 29, 2019
    Publication date: July 30, 2020
    Inventors: JOHN PAUL STRACHAN, SUHAS KUMAR, THOMAS VAN VAERENBERGH
  • Publication number: 20200242447
    Abstract: Recurrent neural networks, and methods therefor, are provided with diagonal and programming fluctuation to find energy global minima. The method may include storing the matrix of weights in memory cells of a crossbar array of a recursive neural network prior to operation of the recursive neural network; altering the weights according to a probability distribution; setting the weights to non-zero values in at least one of the memory cells in a diagonal of the memory cells in the crossbar array; and operating the recursive neural network.
    Type: Application
    Filed: January 29, 2019
    Publication date: July 30, 2020
    Inventors: Suhas Kumar, Thomas Van Vaerenbergh, John Paul Strachan
  • Publication number: 20200218967
    Abstract: A hardware accelerator including a crossbar array programmed to calculate node values of a neural network, the crossbar array comprising a plurality of row lines, a plurality of column lines, and a memory cell coupled between each combination of one row line and one column line. Also, an energy storing element disposed in the crossbar array between each combination of one row line and one column line and a filter that receives information from the energy storing element and provides new information for each node of the neural network.
    Type: Application
    Filed: April 1, 2019
    Publication date: July 9, 2020
    Inventors: John Paul Strachan, Suhas Kumar
  • Patent number: 10706922
    Abstract: In one example in accordance with the present disclosure a device is described. The device includes a cross-bar array of memristive elements. Each memristive element has a conductance value. The device also includes a column of offset elements. An offset element is coupled to a row of memristive elements and has a conductance value. The device also includes a number of accumulation elements. An accumulation element is coupled to a column of memristive elements. The accumulation element collects an intermediate output from the column and subtracts from the intermediate output an output from the column of offset elements.
    Type: Grant
    Filed: January 26, 2016
    Date of Patent: July 7, 2020
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Brent Buchanan, Le Zheng, John Paul Strachan
  • Patent number: 10698975
    Abstract: Example implementations of the present disclosure relate to in situ transposition of the data values in a memory array. An example system may include a non-volatile memory (NVM) array, including a plurality of NVM elements, usable in performance of computations. The example system may include an input engine to input a plurality of data values for storage by a corresponding plurality of original NVM elements. The example system may further include a transposition engine to direct performance of the in situ transposition such that the plurality of data values remains stored by the original NVM elements.
    Type: Grant
    Filed: January 27, 2016
    Date of Patent: June 30, 2020
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Naveen Muralimanohar, Benjamin Feinberg, John Paul Strachan
  • Publication number: 20200193300
    Abstract: Systems are provided for implementing a hardware accelerator. The hardware accelerator emulate a stochastic neural network, and includes a first memristor crossbar array, and a second memristor crossbar array. The first memristor crossbar array can be programmed to calculate node values of the neural network. The nodes values can be calculated in accordance with rules to reduce an energy function associated with the neural network. The second memristor crossbar array is coupled to the first memristor crossbar array and programmed to introduce noise signals into the neural network. The noise signals can be introduced such that the energy function associated with the neural network converges towards a global minimum and modifies the calculated node values.
    Type: Application
    Filed: December 18, 2018
    Publication date: June 18, 2020
    Inventors: SUHAS KUMAR, THOMAS VAN VAERENBERGH, JOHN PAUL STRACHAN
  • Publication number: 20200192598
    Abstract: A method for determining a solution to a constrained optimization problem includes programming a weights matrix of a Hopfield network with a first encoded matrix representation of an initial constrained optimization problem. The method also includes employing the Hopfield network to determine a solution to the initial constrained optimization problem. Additionally, the method includes encoding a plurality of constrained optimization problems associated with a target constrained optimization problem into a plurality of encoded matrix representations each of which are a combination of the first and the second encoded matrix representations. The plurality of encoded matrix representations increases in convergence to the second encoded matrix representation of the target constrained optimization problem sequentially. The method further includes re-programming the weights matrix of the Hopfield network in an iterative manner with the plurality of encoded matrix representations.
    Type: Application
    Filed: March 29, 2019
    Publication date: June 18, 2020
    Inventors: Suhas Kumar, Thomas Van Vaerenbergh, John Paul Strachan
  • Patent number: 10643697
    Abstract: A double bias dot-product engine for vector processing is described. The dot product engine includes a crossbar array having N×M memory elements to store information corresponding to values contained in an N×M matrix, each memory element being a memristive storage device. First and second vector input registers including N voltage inputs, each voltage input corresponding to a value contained in a vector having N×1 values. The vector input registers are connected to the crossbar array to supply voltage inputs to each of N row electrodes at two locations along the electrode. A vector output register is also included to receive voltage outputs from each of M column electrodes.
    Type: Grant
    Filed: October 1, 2018
    Date of Patent: May 5, 2020
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Miao Hu, Jianhua Yang, John Paul Strachan, Ning Ge
  • Publication number: 20200116931
    Abstract: Systems and methods are provided for processing an optical signal. An example system may include a source disposed on a substrate and capable of emitting the optical signal. A first waveguide is formed in the substrate to receive the optical signal. A first coupler is disposed on the substrate to receive a reflected portion of the optical signal. A second waveguide is formed in the substrate to receive the reflected portion from the first coupler. A second coupler is formed in the substrate to mix the optical signal and the reflected portion to form a mixed signal. Photodetectors are formed in the substrate to convert the mixed signal to an electrical signal. A processor is electrically coupled to the substrate and programmed to convert the electrical signal from a time domain to a frequency domain to determine a phase difference between the optical signal and the reflected portion.
    Type: Application
    Filed: December 10, 2019
    Publication date: April 16, 2020
    Inventors: Amit S. Sharma, John Paul Strachan, Marco Fiorentino
  • Patent number: 10621267
    Abstract: A technique includes providing a first set of values to a memristor crossbar array and using the memristor crossbar array to perform a Fourier transformation. Using the memristor crossbar array to perform the Fourier transform includes using the array to apply a Discrete Fourier Transform (DFT) to the first set of values to provide a second set of values.
    Type: Grant
    Filed: January 28, 2016
    Date of Patent: April 14, 2020
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: John Paul Strachan, Miao Hu, R. Stanley Williams, Zhiyong Li
  • Patent number: 10620605
    Abstract: An example finite state machine may include a content-addressable memory. The content-addressable memory may include blocks that respectively store input-terms of the finite state machine. The finite state machine may be configured to, for each received input: select a subset of the blocks of the content addressable memory to enable for searching, the subset being selected based on a current state of the finite state machine, and determine a next state of the finite state machine by searching the currently enabled subset of blocks of the content addressable memory based on the input.
    Type: Grant
    Filed: March 14, 2019
    Date of Patent: April 14, 2020
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Brent Buchanan, John Paul Strachan, Le Zheng
  • Publication number: 20200097440
    Abstract: A method of computing in memory, the method including inputting a packet including data into a computing memory unit having a control unit, loading the data into at least one computing in memory micro-unit, processing the data in the computing in memory micro-unit, and outputting the processed data. Also, a computing in memory system including a computing in memory unit having a control unit, wherein the computing in memory unit is configured to receive a packet having data and a computing in memory micro-unit disposed in the computing in memory unit, the computing in memory micro-unit having at least one of a memory matrix and a logic elements matrix.
    Type: Application
    Filed: September 24, 2018
    Publication date: March 26, 2020
    Inventors: Dejan S. Milojicic, Kirk M. Bresniker, Paolo Faraboschi, John Paul Strachan
  • Publication number: 20200073755
    Abstract: A computer system includes multiple memory array components that include respective analog memory arrays which are sequenced to implement a multi-layer process. An error array data structure is obtained for at least a first memory array component, and from which a determination is made as to whether individual nodes (or cells) of the error array data structure are significant. A determination can be made as to any remedial operations that can be performed to mitigate errors of significance.
    Type: Application
    Filed: August 28, 2018
    Publication date: March 5, 2020
    Inventors: John Paul Strachan, Catherine Graves, Dejan S. Milojicic, Paolo Faraboschi, Martin Foltin, Sergey Serebryakov
  • Patent number: 10580473
    Abstract: A method of obtaining a dot product includes applying a programming signal to a number of capacitive memory devices coupled at a number of junctions formed between a number of row lines and a number of column lines. The programming signal defines a number of values within a matrix. The method further includes applying a vector signal. The vector signal defines a number of vector values to be applied to the capacitive memory devices.
    Type: Grant
    Filed: February 22, 2019
    Date of Patent: March 3, 2020
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Ning Ge, John Paul Strachan, Jianhua Yang, Miao Hu
  • Publication number: 20200042287
    Abstract: Disclosed techniques provide for dynamically changing precision of a multi-stage compute process. For example, changing neural network (NN) parameters on a per-layer basis depending on properties of incoming data streams and per-layer performance of an NN among other considerations. NNs include multiple layers that may each be calculated with a different degree of accuracy and therefore, compute resource overhead (e.g., memory, processor resources, etc.). NNs are usually trained with 32-bit or 16-bit floating-point numbers. Once trained, an NN may be deployed in production. One approach to reduce compute overhead is to reduce parameter precision of NNs to 16 or 8 for deployment. The conversion to an acceptable lower precision is usually determined manually before deployment and precision levels are fixed while deployed.
    Type: Application
    Filed: August 1, 2018
    Publication date: February 6, 2020
    Inventors: Sai Rahul Chalamalasetti, Paolo Faraboschi, Martin Foltin, Catherine Graves, Dejan S. Milojicic, Sergey Serebryakov, John Paul Strachan