Patents by Inventor John Paul Strachan

John Paul Strachan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220375536
    Abstract: Systems, devices, circuits, methods, and non-transitory computer readable media that enable storing and searching arbitrary segments of ranges of analog values are disclosed. Various analog content addressable memory (aCAM) circuit implementations having the capability to store and search outside of a range of values, within any of multiple disjoint ranges, or outside of multiple ranges are disclosed. The disclosed aCAM circuit implementations make searching for complex input features more flexible and efficient, thereby yielding a technological improvement over conventional solutions. In some implementations, an aCAM may include multiple pull-down transistors connected in series to a match line that is pre-charged, in which case, the aCAM detects a match if the match line is not discharged by the pull-down transistors, which occurs if at least one pull-down transistor is in an OFF state. In other implementations, an aCAM includes pass gates connected to a match line to detect a match.
    Type: Application
    Filed: May 20, 2021
    Publication date: November 24, 2022
    Inventors: John Paul Strachan, Can Li, Catherine Graves
  • Publication number: 20220351794
    Abstract: An analog content addressable memory (aCAM) that enables parallel searching of analog ranges of values and generates analog outputs that quantify matches between input data and stored data is disclosed. The input data can be compared with the stored data, and the input data can be determined to match the stored data based on a value associated with the input data being within a range associated with the stored data. The aCAM can generate an analog output that represents a number of matches and a number of mismatches between the input data and the stored data. Based on the analog output, whether the input data matches the stored data and a degree to which the input data matches the stored data can be determined.
    Type: Application
    Filed: April 30, 2021
    Publication date: November 3, 2022
    Inventors: CATHERINE GRAVES, CAN LI, JOHN PAUL STRACHAN
  • Patent number: 11475169
    Abstract: Examples described herein relate to a security system consistent with the disclosure. For instance, the security system may comprise a sensor interface bridge connecting a gateway to an input/output (I/O) card, a Field Programmable Gate Array (FPGA) to scan data to detect an anomaly in the data while the data is in the sensor interface bridge, where a learning neural network accelerator Application-Specific Integrated Circuit (ASIC) is integrated with the FPGA and send the data without an anomaly to the gateway.
    Type: Grant
    Filed: March 4, 2019
    Date of Patent: October 18, 2022
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Martin Foltin, Aalap Tripathy, Harvey Edward White, Jr., John Paul Strachan
  • Patent number: 11462268
    Abstract: Examples disclosed herein relate to digital hash code generation. A digital hash code generating device comprising a plurality of variable conductance elements. Each variable conductance element is coupled to a selected row line and to a selected column line of a crossbar array. Each variable conductance element comprises a conductance from a stochastic distribution of conductance. A plurality of comparator elements and each comparator element is connected to a set of at least two column lines. The plurality of comparator elements generates a hash code in response to a vector input applied to the plurality of row lines of the crossbar array.
    Type: Grant
    Filed: April 30, 2021
    Date of Patent: October 4, 2022
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: John Paul Strachan, Can Li, Catherine Graves
  • Patent number: 11385863
    Abstract: Disclosed techniques provide for dynamically changing precision of a multi-stage compute process. For example, changing neural network (NN) parameters on a per-layer basis depending on properties of incoming data streams and per-layer performance of an NN among other considerations. NNs include multiple layers that may each be calculated with a different degree of accuracy and therefore, compute resource overhead (e.g., memory, processor resources, etc.). NNs are usually trained with 32-bit or 16-bit floating-point numbers. Once trained, an NN may be deployed in production. One approach to reduce compute overhead is to reduce parameter precision of NNs to 16 or 8 for deployment. The conversion to an acceptable lower precision is usually determined manually before deployment and precision levels are fixed while deployed.
    Type: Grant
    Filed: August 1, 2018
    Date of Patent: July 12, 2022
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Sai Rahul Chalamalasetti, Paolo Faraboschi, Martin Foltin, Catherine Graves, Dejan S. Milojicic, Sergey Serebryakov, John Paul Strachan
  • Patent number: 11355899
    Abstract: An optical device includes a light-emitting device integrated with a memory device. The memory device include a first electrode and a second electrode, and the light-emitting device includes a third electrode and the second electrode. In such configuration, a first voltage between the second electrode and the third electrode causes the light-emitting device to emit light of a first wavelength, and a second voltage between the first electrode and the second electrode while the memory device is at OFF state causes the light-emitting device to emit light of a second wavelength shorter than the first wavelength or while the memory device is at ON state causes the light-emitting device to emit light of a third wavelength longer than the first wavelength.
    Type: Grant
    Filed: August 27, 2020
    Date of Patent: June 7, 2022
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Bassem Tossoun, Di Liang, John Paul Strachan
  • Publication number: 20220138204
    Abstract: Encoding of domain logic rules in an analog content addressable memory (aCAM) is disclosed. By encoding domain logic in an aCAM, rapid and flexible search capabilities are enabled, including the capability to search ranges of analog values, fuzzy match capabilities, and optimized parameter search capabilities. This is achieved with low latency by using only a small number of clock cycles at low power. A domain logic ruleset may be represented using various data structures such as decision trees, directed graphs, or the like. These representations can be converted to a table of values, where each table column can be directly mapped to a corresponding row of the aCAM.
    Type: Application
    Filed: October 30, 2020
    Publication date: May 5, 2022
    Inventors: CATHERINE GRAVES, CAN LI, JOHN PAUL STRACHAN, DEJAN S. MILOJICIC, KIMBERLY KEETON
  • Patent number: 11322545
    Abstract: Devices and methods are provided. In one aspect, a device for driving a memristor array includes a substrate including a well having a bottom layer, a first wall and a second wall. The substrate is formed of a strained layer of a first semiconductor material. A vertical JFET is formed in the well. The vertical JFET includes a vertical gate region formed in a middle portion of the well with a gate region height less than a depth of the well. A channel region is formed of an epitaxial layer of a second semiconductor wrapped around the vertical gate region. Vertical source regions are formed on both sides of a first end of the vertical gate region, and vertical drain regions are formed on both sides of a second end of the vertical gate region.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: May 3, 2022
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Amit S. Sharma, John Paul Strachan, Martin Foltin
  • Patent number: 11316537
    Abstract: A fault-tolerant analog computing device includes a crossbar array having a number l rows and a number n columns intersecting the l rows to form l×n memory locations. The l rows of the crossbar array receive an input signal as a vector of length l. The n columns output an output signal as a vector of length n that is a dot product of the input signal and the matrix values defined in the l×n memory locations. Each memory location is programmed with a matrix value. A first set of k columns of the n columns is programmed with continuous analog target matrix values with which the input signal is to be multiplied, where k<n. A second set of m columns of the n columns is programmed with continuous analog matrix values for detecting an error in the output signal that exceeds a threshold error value, where m<n.
    Type: Grant
    Filed: June 3, 2019
    Date of Patent: April 26, 2022
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Ron Roth, John Paul Strachan
  • Patent number: 11315009
    Abstract: An example electronic device includes a crossbar array, row driver circuitry, and column output circuits for each of the column lines of the crossbar array. The crossbar array may include row lines, column lines, and memristors that each are connected between one of the row lines and one of the column lines. The row driver circuitry may be to apply a plurality of analog voltages to a first node during a plurality of time periods, respectively, and, for each of the row lines, selectively connect the row line to the first node during one of the plurality of time periods based on a digital input vector. The column output circuits may each include: an integration capacitor, a switch that is controlled by an integration control signal, and current mirroring circuitry. The current mirroring circuitry may be to, when the switch is closed, flow an integration current to or from an electrode of the integration capacitor whose magnitude mirrors a current flowing on the corresponding column line.
    Type: Grant
    Filed: March 3, 2017
    Date of Patent: April 26, 2022
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Brent Buchanan, Miao Hu, John Paul Strachan
  • Publication number: 20220122646
    Abstract: Examples described herein relate to a decision tree computation system in which a hardware accelerator for a decision tree is implemented in the form of an analog Content Addressable Memory (a-CAM) array. The hardware accelerator accesses a decision tree. The decision tree comprises of multiple paths and each path of the multiple paths includes a set of nodes. Each node of the decision tree is associated with a feature variable of multiple feature variables of the decision tree. The hardware accelerator combines multiple nodes among the set of nodes with a same feature variable into a combined single node. Wildcard values are replaced for feature variables not being evaluated in each path. Each combined single node associated with each feature variable is mapped to a corresponding column in the a-CAM array and the multiple paths of the decision tree to rows of the a-CAM array.
    Type: Application
    Filed: October 15, 2020
    Publication date: April 21, 2022
    Inventors: Catherine Graves, Can Li, Kivanc Ozonat, John Paul Strachan
  • Patent number: 11294763
    Abstract: A computer system includes multiple memory array components that include respective analog memory arrays which are sequenced to implement a multi-layer process. An error array data structure is obtained for at least a first memory array component, and from which a determination is made as to whether individual nodes (or cells) of the error array data structure are significant. A determination can be made as to any remedial operations that can be performed to mitigate errors of significance.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: April 5, 2022
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: John Paul Strachan, Catherine Graves, Dejan S. Milojicic, Paolo Faraboschi, Martin Foltin, Sergey Serebryakov
  • Patent number: 11289162
    Abstract: An analog content addressable memory cell includes a match line, a high side, and a low side. The high side encodes a high bound on a range of values and includes a first three terminal memory device. The first three terminal memory device includes a first gate that sets a high voltage bound of the first three terminal memory device. Specifically, an input voltage applied at the first gate of the first memory device, if higher than the high voltage bound, turns the first memory device ON which discharges the match line. Similarly, the low side encodes a lower bound on a range of values and includes a second three terminal memory device. The second three terminal memory device includes a second gate that sets a low voltage bound of the second three terminal memory device. Specifically, an input voltage applied at the second gate of the second memory device, if lower than the low voltage bound, turns the first memory device ON which discharges the match line.
    Type: Grant
    Filed: April 30, 2020
    Date of Patent: March 29, 2022
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: John Paul Strachan, Catherine Graves, Can Li
  • Publication number: 20220069541
    Abstract: An optical device includes a light-emitting device integrated with a memory device. The memory device include a first electrode and a second electrode, and the light-emitting device includes a third electrode and the second electrode. In such configuration, a first voltage between the second electrode and the third electrode causes the light-emitting device to emit light of a first wavelength, and a second voltage between the first electrode and the second electrode while the memory device is at OFF state causes the light-emitting device to emit light of a second wavelength shorter than the first wavelength or while the memory device is at ON state causes the light-emitting device to emit light of a third wavelength longer than the first wavelength.
    Type: Application
    Filed: August 27, 2020
    Publication date: March 3, 2022
    Inventors: Bassem Tossoun, Di Liang, John Paul Strachan
  • Patent number: 11232352
    Abstract: A circuit for a neuron of a multi-stage compute process is disclosed. The circuit comprises a weighted charge packet (WCP) generator. The circuit may also include a voltage divider controlled by a programmable resistance component (e.g., a memristor). The WCP generator may also include a current mirror controlled via the voltage divider and arrival of an input spike signal to the neuron. WCPs may be created to represent the multiply function of a multiply accumulate processor. The WCPs may be supplied to a capacitor to accumulate and represent the accumulate function. The value of the WCP may be controlled by the length of the spike in signal times the current supplied through the current mirror. Spikes may be asynchronous. Memristive components may be electrically isolated from input spike signals so their programmed conductance is not affected. Positive and negative spikes and WCPs for accumulation may be supported.
    Type: Grant
    Filed: July 17, 2018
    Date of Patent: January 25, 2022
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Brent Buchanan, John Paul Strachan, Le Zheng
  • Publication number: 20210343341
    Abstract: An analog content addressable memory cell includes a match line, a high side, and a low side. The high side encodes a high bound on a range of values and includes a first three terminal memory device. The first three terminal memory device includes a first gate that sets a high voltage bound of the first three terminal memory device. Specifically, an input voltage applied at the first gate of the first memory device, if higher than the high voltage bound, turns the first memory device ON which discharges the match line. Similarly, the low side encodes a lower bound on a range of values and includes a second three terminal memory device. The second three terminal memory device includes a second gate that sets a low voltage bound of the second three terminal memory device. Specifically, an input voltage applied at the second gate of the second memory device, if lower than the low voltage bound, turns the first memory device ON which discharges the match line.
    Type: Application
    Filed: April 30, 2020
    Publication date: November 4, 2021
    Inventors: John Paul Strachan, Catherine Graves, Can Li
  • Publication number: 20210327508
    Abstract: Systems are methods are provided for implementing an analog content addressable memory (analog CAM), which is particularly structured to allow for an amount of variance (fuzziness) in its search operations. The analog CAM may search for approximate matches with the data stored therein, or matches within a defined variance. Circuitry of the analog CAM may include transistor-source lines that receive search-variance parameters, and/or data lines that receive search-variance parameters explicitly within the search input data. The search-variance parameters may include an upper bound and a lower bound that define a range of values within the allotted amount of fuzziness (e.g., deviation from the stored value). The search-variance parameters may program (using analog approaches) the analog CAM to perform searches having a modifiable restrictiveness that is tuned dynamically, as defined by the input search-variance. Thus, highly efficient hardware for complex applications involving fuzziness are enabled.
    Type: Application
    Filed: May 3, 2021
    Publication date: October 21, 2021
    Inventors: Can Li, Catherine Graves, John Paul Strachan
  • Publication number: 20210241068
    Abstract: A convolutional neural network system includes a first part of the convolutional neural network comprising an initial processor configured to process an input data set and store a weight factor set in the first part of the convolutional neural network; and a second part of the convolutional neural network comprising a main computing system configured to process an export data set provided from the first part of the convolutional neural network.
    Type: Application
    Filed: April 30, 2018
    Publication date: August 5, 2021
    Applicant: Hewlett Packard Enterprise Development LP
    Inventors: Martin FOLTIN, John Paul STRACHAN, Sergey SEREBRYAKOV
  • Publication number: 20210240945
    Abstract: In some examples, a device includes a first processing core comprising a resistive memory array to perform an analog computation, and a digital processing core comprising a digital memory programmable with different values to perform different computations responsive to respective different conditions. The device further includes a controller to selectively apply input data to the first processing core and the digital processing core.
    Type: Application
    Filed: April 30, 2018
    Publication date: August 5, 2021
    Applicant: Hewlett Packard Enterprise Development LP
    Inventors: John Paul STRACHAN, Dejan S. MILOJICIC, Martin FOLTIN, Sai Rahul CHALAMALASETTI, Amit S. SHARMA
  • Publication number: 20210225440
    Abstract: A DPE memristor crossbar array system includes a plurality of partitioned memristor crossbar arrays. Each of the plurality of partitioned memristor crossbar arrays includes a primary memristor crossbar array and a redundant memristor crossbar array. The redundant memristor crossbar array includes values that are mathematically related to values within the primary memristor crossbar array. In addition, the plurality of partitioned memristor crossbar arrays includes a block of shared analog circuits coupled to the plurality of partitioned memristor crossbar arrays. The block of shared analog circuits is to determine a dot product value of voltage values generated by at least one partitioned memristor crossbar array of the plurality of partitioned memristor crossbar arrays.
    Type: Application
    Filed: April 6, 2021
    Publication date: July 22, 2021
    Inventors: Amit S. Sharma, John Paul Strachan, Catherine Graves, Suhas Kumar, Craig Warner, Martin Foltin