Patents by Inventor John Paul Tellkamp
John Paul Tellkamp has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240332243Abstract: In examples, a package comprises a semiconductor die having a device side and a bond pad on the device side, a conductive terminal exposed to an exterior of the package, and an electrical fuse. The electrical fuse comprises a conductive ball coupled to the bond pad, and a bond wire coupled to the conductive terminal. The bond wire is stitch-bonded to the conductive ball.Type: ApplicationFiled: June 11, 2024Publication date: October 3, 2024Inventors: Mahmud Halim CHOWDHURY, Amin SIJELMASSI, Murali KITTAPPA, Anindya PODDAR, Honglin GUO, Joe Adam GARCIA, John Paul TELLKAMP
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Patent number: 12009336Abstract: In examples, a package comprises a semiconductor die having a device side and a bond pad on the device side, a conductive terminal exposed to an exterior of the package, and an electrical fuse. The electrical fuse comprises a conductive ball coupled to the bond pad, and a bond wire coupled to the conductive terminal. The bond wire is stitch-bonded to the conductive ball.Type: GrantFiled: July 30, 2021Date of Patent: June 11, 2024Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Mahmud Halim Chowdhury, Amin Sijelmassi, Murali Kittappa, Anindya Poddar, Honglin Guo, Joe Adam Garcia, John Paul Tellkamp
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Publication number: 20230299201Abstract: A packaged multichip isolation device includes leadframe including a first and second die pad, with a first and second lead extending outside a molded body having a downward extending lead bend near their outer ends. A first integrated circuit (IC) die on the first die pad has a first bond pad connected to the first lead that realizes a transmitter or receiver. A second IC die on the second die pad has a second bond pad connected to the second lead that realizes another of the transmitter and receiver. An isolation component is in a signal path of the isolation device including a capacitive isolator, or inductors for transformer isolation on or between the die. A midpoint of the thickness of the die pad is raised above a top level of the leads and in an opposite vertical direction relative to the downward extending bend of the external leads.Type: ApplicationFiled: May 23, 2023Publication date: September 21, 2023Inventors: JOHN PAUL TELLKAMP, ANDREW COUCH
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Patent number: 11658243Abstract: A packaged multichip isolation device includes leadframe including a first and second die pad, with a first and second lead extending outside a molded body having a downward extending lead bend near their outer ends. A first integrated circuit (IC) die on the first die pad has a first bond pad connected to the first lead that realizes a transmitter or receiver. A second IC die on the second die pad has a second bond pad connected to the second lead that realizes another of the transmitter and receiver. An isolation component is in a signal path of the isolation device including a capacitive isolator, or inductors for transformer isolation on or between the die. A midpoint of the thickness of the die pad is raised above a top level of the leads and in an opposite vertical direction relative to the downward extending bend of the external leads.Type: GrantFiled: September 10, 2019Date of Patent: May 23, 2023Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: John Paul Tellkamp, Andrew Couch
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Patent number: 11574884Abstract: An electronic device includes one or more multinode pads having two or more conductive segments spaced from one another on a semiconductor die. A conductive stud bump is selectively formed on portions of the first and second conductive segments to program circuitry of the semiconductor die or to couple a supply circuit to a load circuit. The multinode pad can be coupled to a programming circuit in the semiconductor die to allow programming a programmable circuit of the semiconductor die during packaging. The multinode pad has respective conductive segments coupled to the supply circuit and the load circuit to allow current consumption or other measurements during wafer probe testing in which the first and second conductive segments are separately probed prior to stud bump formation.Type: GrantFiled: January 29, 2021Date of Patent: February 7, 2023Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Suvadip Banerjee, John Paul Tellkamp
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Publication number: 20230036643Abstract: In examples, a package comprises a semiconductor die having a device side and a bond pad on the device side, a conductive terminal exposed to an exterior of the package, and an electrical fuse. The electrical fuse comprises a conductive ball coupled to the bond pad, and a bond wire coupled to the conductive terminal. The bond wire is stitch-bonded to the conductive ball.Type: ApplicationFiled: July 30, 2021Publication date: February 2, 2023Inventors: Mahmud Halim CHOWDHURY, Amin SIJELMASSI, Murali KITTAPPA, Anindya PODDAR, Honglin GUO, Joe Adam GARCIA, John Paul TELLKAMP
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Patent number: 11569153Abstract: A leadframe includes leads or lead terminals, a plurality of folded features including i) support features positioned within an area defined in at least one dimension by the leads or the lead terminals configured for supporting at least one of a die pad and a first pad and a second pad spaced apart from one another, or ii) current carrying features. At least one of the folded features includes a planar portion and a folded edge structure that curves upwards at an angle of at least 45° relative to the planar portion. The folded features are configured to provide an effective increase in thickness to reduce the deformation observed in assembly.Type: GrantFiled: March 16, 2020Date of Patent: January 31, 2023Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Enis Tuncer, John Paul Tellkamp
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Patent number: 11557722Abstract: A Hall-effect sensor package includes and an IC die including a Hall-Effect element and a leadframe including leads on a first side providing a first field generating current (FGC) path including?1 first FGC input pin coupled by a reduced width first curved head over or under the Hall-effect sensor element to ?1 first FGC output pin, and second leads on a second side of the package. Some leads on the second side are attached to bond pads on the IC die including the output of the Hall-effect element. A clip is attached at one end to the first FGC input pin and at another end to a location on the first FGC output pin, having a reduced width second curved head in between that is over or under the Hall-effect sensor element opposite the first head.Type: GrantFiled: January 6, 2021Date of Patent: January 17, 2023Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Ming Li, Yiqi Tang, Jie Chen, Enis Tuncer, Usman Mahmood Chaudhry, Tony Ray Larson, Rajen Manicon Murugan, John Paul Tellkamp, Satyendra Singh Chauhan
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Publication number: 20220246566Abstract: An electronic device includes one or more multinode pads having two or more conductive segments spaced from one another on a semiconductor die. A conductive stud bump is selectively formed on portions of the first and second conductive segments to program circuitry of the semiconductor die or to couple a supply circuit to a load circuit. The multinode pad can be coupled to a programming circuit in the semiconductor die to allow programming a programmable circuit of the semiconductor die during packaging. The multinode pad has respective conductive segments coupled to the supply circuit and the load circuit to allow current consumption or other measurements during wafer probe testing in which the first and second conductive segments are separately probed prior to stud bump formation.Type: ApplicationFiled: January 29, 2021Publication date: August 4, 2022Applicant: Texas Instruments IncorporatedInventors: Suvadip Banerjee, John Paul Tellkamp
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Publication number: 20210305024Abstract: In a described example, a method includes loading at least one package substrate strip including electronic device dies mounted on the at least one package substrate strip into a plasma process chamber; positioning at least one E-field shield in the plasma process chamber spaced from and over the at least one package substrate strip; and plasma cleaning the at least one package substrate strip.Type: ApplicationFiled: March 24, 2020Publication date: September 30, 2021Inventors: Enis Tuncer, John Paul Tellkamp
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Publication number: 20210287970Abstract: A leadframe includes leads or lead terminals, a plurality of folded features including i) support features positioned within an area defined in at least one dimension by the leads or the lead terminals configured for supporting at least one of a die pad and a first pad and a second pad spaced apart from one another, or ii) current carrying features. At least one of the folded features includes a planar portion and a folded edge structure that curves upwards at an angle of at least 45° relative to the planar portion. The folded features are configured to provide an effective increase in thickness to reduce the deformation observed in assembly.Type: ApplicationFiled: March 16, 2020Publication date: September 16, 2021Inventors: Enis Tuncer, John Paul Tellkamp
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Publication number: 20210159403Abstract: A Hall-effect sensor package includes and an IC die including a Hall-Effect element and a leadframe including leads on a first side providing a first field generating current (FGC) path including ?1 first FGC input pin coupled by a reduced width first curved head over or under the Hall-effect sensor element to ?1 first FGC output pin, and second leads on a second side of the package. Some leads on the second side are attached to bond pads on the IC die including the output of the Hall-effect element. A clip is attached at one end to the first FGC input pin and at another end to a location on the first FGC output pin, having a reduced width second curved head in between that is over or under the Hall-effect sensor element opposite the first head.Type: ApplicationFiled: January 6, 2021Publication date: May 27, 2021Inventors: Ming Li, Yiqi Tang, Jie Chen, Enis Tuncer, Usman Mahmood Chaudhry, Tony Ray Larson, Rajen Manicon Murugan, John Paul Tellkamp, Satyendra Singh Chauhan
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Patent number: 10892405Abstract: A Hall-effect sensor package includes and an IC die including a Hall-Effect element and a leadframe including leads on a first side providing a first field generating current (FGC) path including ?1 first FGC input pin coupled by a reduced width first curved head over or under the Hall-effect sensor element to ?1 first FGC output pin, and second leads on a second side of the package. Some leads on the second side are attached to bond pads on the IC die including the output of the Hall-effect element. A clip is attached at one end to the first FGC input pin and at another end to a location on the first FGC output pin, having a reduced width second curved head in between that is over or under the Hall-effect sensor element opposite the first head.Type: GrantFiled: May 7, 2019Date of Patent: January 12, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Ming Li, Yiqi Tang, Jie Chen, Enis Tuncer, Usman Mahmood Chaudhry, Tony Ray Larson, Rajen Manicon Murugan, John Paul Tellkamp, Satyendra Singh Chauhan
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Publication number: 20200357987Abstract: A Hall-effect sensor package includes and an IC die including a Hall-Effect element and a leadframe including leads on a first side providing a first field generating current (FGC) path including ?1 first FGC input pin coupled by a reduced width first curved head over or under the Hall-effect sensor element to ?1 first FGC output pin, and second leads on a second side of the package. Some leads on the second side are attached to bond pads on the IC die including the output of the Hall-effect element. A clip is attached at one end to the first FGC input pin and at another end to a location on the first FGC output pin, having a reduced width second curved head in between that is over or under the Hall-effect sensor element opposite the first head.Type: ApplicationFiled: May 7, 2019Publication date: November 12, 2020Inventors: Ming Li, Yiqi Tang, Jie Chen, Enis Tuncer, Usman Mahmood Chaudhry, Tony Ray Larson, Rajen Manicon Murugan, John Paul Tellkamp, Satyendra Singh Chauhan
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Publication number: 20200118899Abstract: A semiconductor isolation package includes a leadframe that includes a plurality of leadframe leads. At least one of the plurality of leadframe leads includes a lead body having a first end that comprises an external pin portion and a second end. The lead body has a leg portion coupled to a central lead portion that is coupled to an edge bend portion. The edge bend portion is formed by a first bend on the lead body proximate the second end between the central lead portion and edge bend portion. The first bend is in the direction of the first end on the leg portion. The edge bend assists in shielding electronic fields. Other aspects are presented.Type: ApplicationFiled: December 10, 2019Publication date: April 16, 2020Inventors: John Paul Tellkamp, Chang-Yen Ko
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Publication number: 20200006562Abstract: A packaged multichip isolation device includes leadframe including a first and second die pad, with a first and second lead extending outside a molded body having a downward extending lead bend near their outer ends. A first integrated circuit (IC) die on the first die pad has a first bond pad connected to the first lead that realizes a transmitter or receiver. A second IC die on the second die pad has a second bond pad connected to the second lead that realizes another of the transmitter and receiver. An isolation component is in a signal path of the isolation device including a capacitive isolator, or inductors for transformer isolation on or between the die. A midpoint of the thickness of the die pad is raised above a top level of the leads and in an opposite vertical direction relative to the downward extending bend of the external leads.Type: ApplicationFiled: September 10, 2019Publication date: January 2, 2020Inventors: JOHN PAUL TELLKAMP, ANDREW COUCH
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Patent number: 10439065Abstract: A packaged multichip isolation device includes leadframe including a first and second die pad, with a first and second lead extending outside a molded body having a downward extending lead bend near their outer ends. A first integrated circuit (IC) die on the first die pad has a first bond pad connected to the first lead that realizes a transmitter or receiver. A second IC die on the second die pad has a second bond pad connected to the second lead that realizes another of the transmitter and receiver. An isolation component is in a signal path of the isolation device including a capacitive isolator, or inductors for transformer isolation on or between the die. A midpoint of the thickness of the die pad is raised above a top level of the leads and in an opposite vertical direction relative to the downward extending bend of the external leads.Type: GrantFiled: May 9, 2018Date of Patent: October 8, 2019Assignee: Texas Instruments IncorporatedInventors: John Paul Tellkamp, Andrew Couch
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Publication number: 20190109233Abstract: A packaged multichip isolation device includes leadframe including a first and second die pad, with a first and second lead extending outside a molded body having a downward extending lead bend near their outer ends. A first integrated circuit (IC) die on the first die pad has a first bond pad connected to the first lead that realizes a transmitter or receiver. A second IC die on the second die pad has a second bond pad connected to the second lead that realizes another of the transmitter and receiver. An isolation component is in a signal path of the isolation device including a capacitive isolator, or inductors for transformer isolation on or between the die. A midpoint of the thickness of the die pad is raised above a top level of the leads and in an opposite vertical direction relative to the downward extending bend of the external leads.Type: ApplicationFiled: May 9, 2018Publication date: April 11, 2019Inventors: JOHN PAUL TELLKAMP, ANDREW COUCH
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Publication number: 20190109061Abstract: In one instance, a semiconductor isolation package includes a leadframe that includes a plurality of leadframe leads. At least one of the plurality of leadframe leads includes a lead body having a first end that comprises an external pin portion and a second end. The lead body has a leg portion coupled to a central lead portion that is coupled to an edge bend portion. The edge bend portion is formed by a first bend on the lead body proximate the second end between the central lead portion and edge bend portion. The first bend is in the direction of the first end on the leg portion. The edge bend assists in shielding electronic fields. Other aspects are presented.Type: ApplicationFiled: July 5, 2018Publication date: April 11, 2019Inventors: John Paul Tellkamp, Chang-Yen Ko
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Patent number: 9239353Abstract: A method of testing an integrated circuit clearance distance device (“ICCDD”) having a predetermined clearance distance in air requirement and a predetermined isolation voltage limit including calculating a value of the breakdown voltage at the predetermined clearance distance for at least one gas; and selecting a gas in which the ICCDD has a breakdown voltage that is less than the predetermined isolation voltage.Type: GrantFiled: June 20, 2013Date of Patent: January 19, 2016Assignee: TEXAS INSTRUMENTS INCORPORATEDInventor: John Paul Tellkamp