Patents by Inventor John R. Sporre

John R. Sporre has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10833190
    Abstract: Embodiments are directed to methods and resulting structures for a vertical field effect transistor (VFET) having a super long channel. A pair of semiconductor fins is formed on a substrate. A semiconductor pillar is formed between the semiconductor fins on the substrate. A region that extends under all of the semiconductor fins and under part of the semiconductor pillar is doped. A conductive gate is formed over a channel region of the semiconductor fins and the semiconductor pillar. A surface of the semiconductor pillar serves as an extended channel region when the gate is active.
    Type: Grant
    Filed: July 19, 2019
    Date of Patent: November 10, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Marc A. Bergendahl, Kangguo Cheng, Gauri Karve, Fee Li Lie, Eric R. Miller, John R. Sporre, Sean Teehan
  • Publication number: 20200294803
    Abstract: A method of forming adjacent fin field effect transistor devices is provided. The method includes forming at least two vertical fins in a column on a substrate, depositing a gate dielectric layer on the vertical fins, and depositing a work function material layer on the gate dielectric layer. The method further includes depositing a protective liner on the work function material layer, and forming a fill layer on the protective liner. The method further includes removing a portion of the fill layer to form an opening between an adjacent pair of two vertical fins, where the opening exposes a portion of the protective liner. The method further includes depositing an etch-stop layer on the exposed surfaces of the fill layer and protective liner, forming a gauge layer in the opening to a predetermined height, and removing the exposed portion of the etch-stop layer to form an etch-stop segment.
    Type: Application
    Filed: March 14, 2019
    Publication date: September 17, 2020
    Inventors: Wenyu Xu, Stuart A. Sieg, Ruilong Xie, John R. Sporre
  • Publication number: 20200266284
    Abstract: A method and structures are used to fabricate a nanosheet semiconductor device. Nanosheet fins including nanosheet stacks including alternating silicon (Si) layers and silicon germanium (SiGe) layers are formed on a substrate and etched to define a first end and a second end along a first axis between which each nanosheet fin extends parallel to every other nanosheet fin. The SiGe layers are undercut in the nanosheet stacks at the first end and the second end to form divots, and a dielectric is deposited in the divots. The SiGe layers between the Si layers are removed before forming source and drain regions of the nanosheet semiconductor device such that there are gaps between the Si layers of each nanosheet stack, and the dielectric anchors the Si layers. The gaps are filled with an oxide that is removed after removing the dummy gate and prior to forming the replacement gate.
    Type: Application
    Filed: February 21, 2020
    Publication date: August 20, 2020
    Applicant: Tessera, Inc.
    Inventors: Marc A. Bergendahl, Kangguo Cheng, Fee Li Lie, Eric R. Miller, John R. Sporre, Sean Teehan
  • Patent number: 10741752
    Abstract: Methods of forming the MRAM generally include forming an array of MTJ having sub-lithographic dimensions. The array can be formed by providing a substrate including a MTJ material stack including a reference ferromagnetic layer, a tunnel barrier layer, and a free ferromagnetic layer on an opposite side of the tunnel barrier layer. A hardmask layer is deposited onto the MTJ material stack. A first sidewall spacer is formed on the hardmask layer in a first direction. A second sidewall spacer is formed over the first sidewall in a second direction, wherein the first direction is orthogonal to the second direction. The second sidewall spacer intersects the first sidewall spacer. The first sidewall spacer is processed using the second sidewall spacer as mask to form a pattern of oxide pillars having sub-lithographic dimensions. The pattern of oxide pillars are transferred into the MTJ stack to form the array.
    Type: Grant
    Filed: January 6, 2020
    Date of Patent: August 11, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Anthony J. Annunziata, Babar A. Khan, Chandrasekharan Kothandaraman, John R. Sporre
  • Publication number: 20200243648
    Abstract: Semiconductor devices include a first semiconductor fin. A first gate stack is formed over the first semiconductor fin. Source and drain regions are formed on respective sides of the first gate stack. An interlayer dielectric is formed around the first gate stack. A gate cut plug is formed from a dielectric material at an end of the first gate stack.
    Type: Application
    Filed: February 21, 2020
    Publication date: July 30, 2020
    Applicant: TESSERA, INC.
    Inventors: John R. Sporre, Siva Kanakasabapathy, Andrew M. Greene, Jeffrey Shearer, Nicole A. Saulnier
  • Publication number: 20200235094
    Abstract: A method of forming a semiconductor device that includes forming a trench adjacent to a gate structure to expose a contact surface of one of a source region and a drain region. A sacrificial spacer may be formed on a sidewall of the trench and on a sidewall of the gate structure. A metal contact may then be formed in the trench to at least one of the source region and the drain region. The metal contact has a base width that is less than an upper surface width of the metal contact. The sacrificial spacer may be removed, and a substantially conformal dielectric material layer can be formed on sidewalls of the metal contact and the gate structure. Portions of the conformally dielectric material layer contact one another at a pinch off region to form an air gap between the metal contact and the gate structure.
    Type: Application
    Filed: March 30, 2020
    Publication date: July 23, 2020
    Applicant: TESSERA, INC.
    Inventors: Marc A. Bergendahl, Kangguo Cheng, Fee Li Lie, Eric R. Miller, John R. Sporre, Sean Teehan
  • Publication number: 20200219874
    Abstract: The present invention provides fin cut techniques in a replacement gate process for finFET fabrication. In one aspect, a method of forming a finFET employs a dummy gate material to pin a lattice constant of patterned fins prior to a fin cut thereby preventing strain relaxation. A dielectric fill in a region of the fin cut (below the dummy gates) reduces an aspect ratio of dummy gates formed from the dummy gate material in the fin cut region, thereby preventing collapse of the dummy gates. FinFETs formed using the present process are also provided.
    Type: Application
    Filed: March 3, 2020
    Publication date: July 9, 2020
    Inventors: Andrew M. Greene, Balasubramanian Pranatharthiharan, Sivananda K. Kanakasabapathy, John R. Sporre
  • Publication number: 20200194563
    Abstract: Semiconductor devices include a first dielectric layer formed over a source and drain region. A second dielectric layer is formed over the first dielectric layer. The second dielectric layer has an internal structure that is the result of a thermal oxidation process and has a higher quality than an internal structure of the first dielectric layer. A gate stack is positioned through the first and second dielectric layers.
    Type: Application
    Filed: February 21, 2020
    Publication date: June 18, 2020
    Inventors: Kangguo Cheng, Andrew M. Greene, John R. Sporre, Peng Xu
  • Patent number: 10658473
    Abstract: Semiconductor devices include a first dielectric layer formed over a source and drain region. A second dielectric layer is formed over the first dielectric layer, the second dielectric layer having a flat, non-recessed top surface. A gate stack passes vertically through the first and second dielectric layers to contact the source and drain regions and an underlying substrate.
    Type: Grant
    Filed: July 12, 2018
    Date of Patent: May 19, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Andrew M. Greene, John R. Sporre, Peng Xu
  • Publication number: 20200144495
    Abstract: Methods of forming the MRAM generally include forming an array of MTJ having sub-lithographic dimensions. The array can be formed by providing a substrate including a MTJ material stack including a reference ferromagnetic layer, a tunnel barrier layer, and a free ferromagnetic layer on an opposite side of the tunnel barrier layer. A hardmask layer is deposited onto the MTJ material stack. A first sidewall spacer is formed on the hardmask layer in a first direction. A second sidewall spacer is formed over the first sidewall in a second direction, wherein the first direction is orthogonal to the second direction. The second sidewall spacer intersects the first sidewall spacer. The first sidewall spacer is processed using the second sidewall spacer as mask to form a pattern of oxide pillars having sub-lithographic dimensions. The pattern of oxide pillars are transferred into the MTJ stack to form the array.
    Type: Application
    Filed: January 6, 2020
    Publication date: May 7, 2020
    Inventors: Anthony J. Annunziata, Babar A. Khan, Chandrasekharan Kothandaraman, John R. Sporre
  • Patent number: 10629699
    Abstract: Embodiments are directed to methods of forming a semiconductor device and resulting structures for improving gate height control and providing interlayer dielectric (ILD) protection during replacement metal gate (RMG) processes. The method includes forming a semiconductor fin on a substrate. A sacrificial gate is formed over a channel region of the semiconductor fin, and an oxide hard mask is formed on a surface of the sacrificial gate. An interlayer dielectric (ILD) is formed adjacent to the sacrificial gate. The ILD is recessed below a surface of the oxide hard mask, and a nitride layer is formed on a surface of the recessed ILD.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: April 21, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Andrew M. Greene, John R. Sporre, Stan Tsai, Ruilong Xie
  • Patent number: 10629698
    Abstract: Sacrificial gate structures having an aspect ratio of greater than 5:1 are formed on a substrate. In some embodiments, each sacrificial gate structure straddles a portion of a semiconductor fin that is present on the substrate. An anchoring element is formed orthogonal to each sacrificial gate structure rendering the sacrificial gate structures mechanically stable. After formation of a planarization dielectric layer, each anchoring element can be removed and thereafter each sacrificial gate structure can be replaced with a functional gate structure.
    Type: Grant
    Filed: November 2, 2017
    Date of Patent: April 21, 2020
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Ryan O. Jung, Fee Li Lie, Jeffrey C. Shearer, John R. Sporre, Sean Teehan
  • Patent number: 10622352
    Abstract: The present invention provides fin cut techniques in a replacement gate process for finFET fabrication. In one aspect, a method of forming a finFET employs a dummy gate material to pin a lattice constant of patterned fins prior to a fin cut thereby preventing strain relaxation. A dielectric fill in a region of the fin cut (below the dummy gates) reduces an aspect ratio of dummy gates formed from the dummy gate material in the fin cut region, thereby preventing collapse of the dummy gates. FinFETs formed using the present process are also provided.
    Type: Grant
    Filed: January 25, 2017
    Date of Patent: April 14, 2020
    Assignee: International Business Machines Corporation
    Inventors: Andrew M. Greene, Balasubramanian Pranatharthiharan, Sivananda K. Kanakasabapathy, John R. Sporre
  • Patent number: 10615269
    Abstract: A method and structures are used to fabricate a nanosheet semiconductor device. Nanosheet fins including nanosheet stacks including alternating silicon (Si) layers and silicon germanium (SiGe) layers are formed on a substrate and etched to define a first end and a second end along a first axis between which each nanosheet fin extends parallel to every other nanosheet fin. The SiGe layers are undercut in the nanosheet stacks at the first end and the second end to form divots, and a dielectric is deposited in the divots. The SiGe layers between the Si layers are removed before forming source and drain regions of the nanosheet semiconductor device such that there are gaps between the Si layers of each nanosheet stack, and the dielectric anchors the Si layers. The gaps are filled with an oxide that is removed after removing the dummy gate and prior to forming the replacement gate.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: April 7, 2020
    Assignee: Terresa, Inc.
    Inventors: Marc A. Bergendahl, Kangguo Cheng, Fee Li Lie, Eric R. Miller, John R. Sporre, Sean Teehan
  • Patent number: 10607991
    Abstract: A method of forming a semiconductor device that includes forming a trench adjacent to a gate structure to expose a contact surface of one of a source region and a drain region. A sacrificial spacer may be formed on a sidewall of the trench and on a sidewall of the gate structure. A metal contact may then be formed in the trench to at least one of the source region and the drain region. The metal contact has a base width that is less than an upper surface width of the metal contact. The sacrificial spacer may be removed, and a substantially conformal dielectric material layer can be formed on sidewalls of the metal contact and the gate structure. Portions of the conformally dielectric material layer contact one another at a pinch off region to form an air gap between the metal contact and the gate structure.
    Type: Grant
    Filed: June 7, 2018
    Date of Patent: March 31, 2020
    Assignee: Tessera, Inc.
    Inventors: Marc A. Bergendahl, Kangguo Cheng, Fee Li Lie, Eric R. Miller, John R. Sporre, Sean Teehan
  • Patent number: 10600868
    Abstract: Semiconductor devices include a first semiconductor fin. A first gate stack is formed over the first semiconductor fin. Source and drain regions are formed on respective sides of the first gate stack. An interlayer dielectric is formed around the first gate stack. A gate cut plug is formed from a dielectric material at an end of the first gate stack.
    Type: Grant
    Filed: January 10, 2019
    Date of Patent: March 24, 2020
    Assignee: Tessera, Inc.
    Inventors: John R. Sporre, Siva Kanakasabapathy, Andrew M. Greene, Jeffrey Shearer, Nicole A. Saulnier
  • Patent number: 10593555
    Abstract: The manufacture of a FinFET device includes the formation of a composite sacrificial gate. The composite sacrificial gate includes a sacrificial gate layer such as a layer of amorphous silicon, and an etch selective layer such as a layer of silicon germanium. The etch selective layer, which underlies the sacrificial gate layer, enables the formation of a gate cut opening having a controlled critical dimension that extends through the composite sacrificial gate.
    Type: Grant
    Filed: March 20, 2018
    Date of Patent: March 17, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Qun Gao, Naved Siddiqui, Ankur Arya, John R Sporre
  • Publication number: 20200083334
    Abstract: Methods of forming semiconductor devices include forming a lower dielectric layer, to a height below a height of a dummy gate hardmask disposed across multiple device regions, by forming a dielectric fill to the height of a dummy gate and etching the dielectric fill back. A dummy gate structure includes the dummy gate and the dummy gate hardmask. A protective layer is formed on the dielectric layer to the height of the dummy gate hardmask. The dummy gate hardmask is etched back to expose the dummy gate.
    Type: Application
    Filed: November 13, 2019
    Publication date: March 12, 2020
    Inventors: Kangguo Cheng, Andrew M. Greene, John R. Sporre, Peng Xu
  • Publication number: 20200066519
    Abstract: A method for semiconductor processing includes removing, from a first region of a semiconductor device, a middle layer and a bottom layer of a trilayer structure including a photoresist layer to expose at least one first structure. A top layer of the trilayer structure in a second region of the semiconductor device is removed during the removal of the bottom layer in the first region. The method further includes, after removing the middle and bottom layers in the first region, filling the first region to protect the at least one first structure.
    Type: Application
    Filed: November 1, 2019
    Publication date: February 27, 2020
    Inventors: Muthumanickam Sankarapandian, Soon-Cheon Seo, Indira P. Seshadri, John R. Sporre
  • Patent number: 10573745
    Abstract: Embodiments are directed to methods and resulting structures for a vertical field effect transistor (VFET) having a super long channel. A pair of semiconductor fins is formed on a substrate. A semiconductor pillar is formed between the semiconductor fins on the substrate. A region that extends under all of the semiconductor fins and under part of the semiconductor pillar is doped. A conductive gate is formed over a channel region of the semiconductor fins and the semiconductor pillar. A surface of the semiconductor pillar serves as an extended channel region when the gate is active.
    Type: Grant
    Filed: May 23, 2017
    Date of Patent: February 25, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Marc A. Bergendahl, Kangguo Cheng, Gauri Karve, Fee Li Lie, Eric R. Miller, John R. Sporre, Sean Teehan