Patents by Inventor John S. Farnbach

John S. Farnbach has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4780689
    Abstract: An improved amplifier input circuit for use as the input stage for a current feedback amplifier to reduce offset and limit overload currents. The circuit includes first and second bias current supplies, first and second diodes having anode and cathode terminals, a PNP transistor and a NPN transistor, first and second input terminals, and first and second current sense terminals. Currents flowing through the sense terminals are sensitive to an input current in the first input terminal. Bias currents from the first and second bias current supplies are divided, respectively, between the PNP transistor and first diode, and the NPN transistor and second diode. The base terminals of the transistors are connected in common to the second input terminal. Other embodiments are also described.
    Type: Grant
    Filed: July 20, 1987
    Date of Patent: October 25, 1988
    Assignee: Comlinear Corporation
    Inventors: Kenneth R. Saller, John S. Farnbach
  • Patent number: 4065915
    Abstract: A binary counting system applicable for a variety of applications, but particularly suitable for use in a display actuator for an electronic clock, includes circuit means for counting through a sequence of more than ten states which represent a sequence of consecutive decimal numbers in a manner that all the binary logic states representing decimal numbers with a common unit's digit are part of an exclusive sub-cube of a minterm map common only to that unit's digit.
    Type: Grant
    Filed: July 2, 1975
    Date of Patent: January 3, 1978
    Inventor: John S. Farnbach