Abstract: An apparatus and method for fetching instructions in an information handling system operating at a predetermined number of cycles per second includes an instruction cache for storing instructions to be fetched. Branch target calculators are operably coupled to instruction queues and to a fetch address selector for determining, in parallel, if instructions in the instruction queues are branch instructions and for providing, in parallel, a target address for each of the instruction queues to the fetch address selector such that the fetch address selector can provide the instruction cache with one of the plurality of target addresses as the next fetch address. Decoding of instructions, calculating the target addresses of branch instructions, and resolving branch instructions are performed in parallel instead of sequentially and, in this manner, back-to-back taken branches can be executed at a rate of one per cycle.

Abstract: A system and method is disclosed for saving power dissipated during the recharge of large arrays, such a domino SRAMS, by activating only the recharge circuits for the parts of the array that was accessed during the previous cycle. This is accomplished by intercepting the recharge signals and deactivating the signals for the non-accessed portions of the array.

Abstract: A system and method for improving a domino SRAM that eliminates the need for additional transistors in series with evaluation transistors. The regular structure inherent in RAM arrays is used to minimize both the effective recharge cycle time and the recharge power required to recharge the various levels of domino SRAM circuits. Using a clock signal as a reference, recharge signals are timed to each other and to other functional signals. By adjusting buffers and wiring delays associated with each recharge signal, the recharge signals sent to each level of logic are delayed until the recharge of the previous level is complete.

Abstract: A method and system are provided for transferring information between multiple buses. Information is transferred through a first bus between multiple first bus devices. Information is transferred through a second bus between multiple second bus devices. Information is transferred through logic between the first and second buses. Using the logic, an action of a first bus device is enabled in response to a condition in which a second bus device waits for the action while the first bus device waits for a separate action on the second bus.

Abstract: The present invention is directed toward an combined decoder/adder circuit which provides faster access to a cache in a microprocessor than implementations which include an adder circuit which is followed by a decoder circuit. By decoding the upper order bits of a first operand and then rotating the upper order bits of the first operand by the upper order bits of a second operand, followed by an additional shift by one which is enabled by a carry generator the overall speed of the critical path is greatly increased. Accordingly, the time needed for generating an effective address (EA) and therefore accessing the cache is significantly decreased. The present invention has significant utility in microprocessors in which the word line decode is the critical path.

Abstract: A method for managing a data transfer between a first device and an allocated portion of common memory including the steps of receiving a reallocation request of the allocated portion of common memory from a second device, receiving a veto of the requested reallocation from the first device, and delaying the reallocation request. In addition, a method for transferring data between a peripheral device and a common memory in a virtual memory system including the steps of instructing the peripheral device to transfer data with an allocated portion of the common memory, requesting a reallocation of the allocated portion of the common memory, and receiving a veto of the requested reallocation from the peripheral device in response to the instructed data transfer.

Abstract: A method and system for distributed instruction address translation in a multiscalar data processing system having multiple processor units for executing multiple tasks, instructions and data stored within memory at real addresses therein and a fetcher unit for fetching and dispatching instructions to the processor units. A memory management unit (MMU) is established which includes a translation buffer and translation algorithms for implementing page table and address block type translations of every effective address within the data processing system into real addresses within memory. A translation array, which includes a small number of translation objects for translating effective addresses into real addresses, is then established within the fetcher unit. The translation objects are periodically and selectively varied, utilizing the translation capability of the memory management unit (MMU), in response to a failure to translate an effective address into a real address within the fetcher unit.

Abstract: Translation lookaside buffers (TLB) are often utilized in the data processing system to efficiently translate an effective or virtual address to a real address within system memory. In systems which include multiple processors which may all access system memory, each processor may include a translation lookaside buffer (TLB) for translating effective addresses to real addresses and coherency between all translation lookaside buffers (TLB) must therefore be maintained. The method and system disclosed herein may be utilized to broadcast a unique bus structure in response to an execution of a translation lookaside buffer invalidate (TLBI) instruction by any processor within a multiprocessor system. The bus structure is accepted by other processors along the bus only in response to an absence of a pending translation lookaside buffer invalidate (TLBI) instruction within each processor.

Abstract: A memory circuit including a bit addressable binary data memory in which the data is stored in a plurality of dimensional directions and a circuit for accessing a group of the data in the memory in at least two of the dimensional directions and for moving the data to a different dimensional location while maintaining the data within the group. Also provided is a means for accessing the data by incrementally or decrementally addressing the data in at least one of the directions. The accessing circuitry is further used to perform bit block transfers of data within the memory. The accessing circuit also provides for horizontal or vertical access during a read operation while orthogonally rotating the data by 90 degrees during a following write operation.

Abstract: A system to display an image including a first memory for storing picture data representing the image attribute data to qualify the picture data. The attribute data includes embedded synchronization data. The system further includes a circuit that produces the image by scanning the picture data qualified by the attribute data onto to a display in accordance with the synchronization data. This invention further provides for storing the synchronization data within the attribute data enabling the synchronization data to be programmable but only requiring update of the synchronization data when the synchronization data is to be changed. The memory includes two buffers wherein one buffer is loaded with attribute and synchronization data while the other buffer is being read. After the other buffer is read, the buffers are toggled such so that the loaded buffer is read to provide the attribute and synchronization data while the previously read buffer is loaded with new attribute and synchronization data.

Abstract: A memory array associated with a display can be accessed in either one of two substantially orthogonal directions. The memory array is structured so that it may be accessed, such as for reading or writing, in either the horizontal or vertical direction. Pel position representations in the array are arranged so that vertically sequential pel positions in a given column are represented by data in sequential memory modules rather than by data in the same memory module. Likewise, horizontally sequential pels in a given row are represented by data in sequential modules rather than in the same module. The memory array is comprised of a plurality of separate memory modules and is structured so that both x and y directional accessing into and out of the array is accomplished on a bit addressable x,y field. This enables any bit string in the array to be addressed and to be read from or written into the array in either the x or y direction.

Abstract: A cursor generation circuit for an image display system that includes a storing circuit for storing image data. The storing circuit includes a first port to provide access to the image data to the display system and a second port to provide access to the image data to a display device for displaying the image data. A combining circuit is further provided to combine the image data with cursor data in the storing circuit when the storing circuit is being accessed by the display device. However, the combining circuit removes the cursor data from the image data when the image data is being accessed by the display system through the first port.