Patents by Inventor John Samuel Liberty

John Samuel Liberty has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11372703
    Abstract: A memory controller receives, via a first interface, a first read request requesting a requested data granule. Based on receipt of the first read request, the memory controller transmits, via a second interface, a second read request to initiate access of the requested data granule from a system memory. Based on a determination to schedule accelerated data delivery and receipt by the memory controller of a data scheduling indication that indicates a timing of future delivery of the requested data granule, the memory controller requests, prior to receipt of the requested data granule, permission to transmit the requested data granule on the system interconnect fabric. Based on receipt of the requested data granule at the indicated timing and a grant of the permission to transmit, the memory controller initiates transmission of the requested data granule on the system interconnect fabric and transmits an error indication for the requested data granule.
    Type: Grant
    Filed: February 19, 2021
    Date of Patent: June 28, 2022
    Assignee: International Business Machines Corporation
    Inventors: John Samuel Liberty, Brad William Michael, Stephen J. Powell, Nicholas Steven Rolfe
  • Patent number: 8838950
    Abstract: The present invention provides for authenticating code and/or data and providing a protected environment for execution. The present invention provides for dynamically partitioning and un-partitioning a local store for the authentication of code or data. The local store is partitioned into an isolated and non-isolated section. Code or data is loaded into the isolated section. The code or data is authenticated in the isolated section of the local store. After authentication, the code is executed. After execution, the memory within the isolated region of the attached processor unit is erased, and the attached processor unit de-partitions the isolated section within the local store.
    Type: Grant
    Filed: June 23, 2003
    Date of Patent: September 16, 2014
    Assignee: International Business Machines Corporation
    Inventors: David John Craft, Michael Norman Day, Harm Peter Hofstee, Charles Ray Johns, John Samuel Liberty
  • Patent number: 7986330
    Abstract: A method, apparatus, and computer implemented instructions for generating antialiased lines for display in a data processing system. Graphics data is received for display, wherein the graphics data includes primitives defining lines. A gamma correction is applied to the graphics data on a per primitive basis to form antialiased lines. The antialiased lines are displayed.
    Type: Grant
    Filed: April 12, 2001
    Date of Patent: July 26, 2011
    Assignee: International Business Machines Corporation
    Inventors: Daniel Alan Brokenshire, Bruce David D'Amora, Gordon Clyde Fossum, Charles Ray Johns, John Samuel Liberty, Brad William Michael
  • Patent number: 7890561
    Abstract: A random number generator, a method, and a computer program product are provided for producing a random number seed. Each oscillator within an array of oscillators operates at a different frequency. The operating frequencies of each oscillator are not harmonically related, such that no integer multiple exists between the frequencies of any two oscillators. In one embodiment, the outputs of the array of oscillators connect to a multiple input latch. The multiple input latch also receives a sample signal, which is a clock signal. The clock signal samples the outputs of the array of oscillators, and the multiple input latch in conjunction with the random number determination logic (“RNDL”) produces a digital output (0 or 1) for each oscillator within the array. The RNDL uses these digital outputs to create a random number seed.
    Type: Grant
    Filed: August 16, 2005
    Date of Patent: February 15, 2011
    Assignee: International Business Machines Corporation
    Inventors: David William Boerstler, Eskinder Hailu, Harm Peter Hofstee, John Samuel Liberty
  • Patent number: 7836222
    Abstract: An apparatus which uses channel counters in combination with channel count read instructions as a means of providing information that data in a given channel is valid or has not been previously read. The counter may also, in the situation of the channel being defined as blocking, be used to prevent the unintentional overwriting of data in a register used by the channel or, alternatively, prevent further communications with the device assigned to that channel when a given count occurs. Intelligent external devices may also use channel count read instructions sent to the counting mechanism for reading from and writing to the channel.
    Type: Grant
    Filed: June 26, 2003
    Date of Patent: November 16, 2010
    Assignee: International Business Machines Corporation
    Inventors: Michael Norman Day, Brian King Flachs, Harm Peter Hofstee, Charles Ray Johns, John Samuel Liberty
  • Patent number: 7279996
    Abstract: A method and apparatus is provided for testing the logic functionality and electrical continuity of a ring oscillator comprising an odd number of inverters connected to form a closed loop. In the method and apparatus, a known value is forced through the ring oscillator, to test the complete circuit path thereof. Thus, a low overhead deterministic test of the functionality of the ring oscillator is provided. In a useful embodiment of the invention, a method is provided for testing functionality and electrical continuity in a ring oscillator, wherein a first test device is inserted between the input of a first inverter and the output of an adjacent second inverter. The first test device is then operated to apply first and second test bits as input test signals to the first inverter input.
    Type: Grant
    Filed: August 16, 2005
    Date of Patent: October 9, 2007
    Assignee: International Business Machines Corporation
    Inventors: David William Boerstler, Eskinder Hailu, Harm Peter Hofstee, John Samuel Liberty
  • Patent number: 7233212
    Abstract: A circuit topology which can be used to create an array of individually tuned oscillators operating at different frequencies determined by common control inputs and an easily managed variation in design dimensions of several components is provided. An array of oscillators are provided arranged in columns and rows. Each oscillator in a column is unique from the other oscillators in the column based on number of stages in the oscillator and fanout so that each oscillator will operate at a unique frequency. Oscillators of different columns within the array may differ by a common setting of the selects to these oscillators and the physical ordering of the oscillators in the column to further reduce the possibility of injection locking. A base delay cell provides selects to each column of oscillators such that each column may be programmed to operate at a different frequency from its neighbors.
    Type: Grant
    Filed: March 31, 2005
    Date of Patent: June 19, 2007
    Assignee: International Business Machines Corporation
    Inventors: David William Boerstler, Eskinder Hailu, Harm Peter Hofstee, John Samuel Liberty
  • Patent number: 7197655
    Abstract: Disclosed is an apparatus which places computer program instructions into instruction channels in accordance with predefined criteria such that at least some external event instructions are placed in a special “blocking channel.” The number of instructions, in a channel, is monitored in channel specific counters. When a computer processor is awaiting a response from an external entity event (in other words, is blocked from proceeding with the operation the PU is attempting), as signified by the blocking counter being at a predetermined value, the entire PU or at least processor auxiliary components that would be idle, such as math logic, while awaiting an external event response, are deactivated to save power until an awaited external event response is received.
    Type: Grant
    Filed: June 26, 2003
    Date of Patent: March 27, 2007
    Assignee: International Business Machines Corporation
    Inventors: Brian King Flachs, John Samuel Liberty, Harm Peter Hofstee
  • Patent number: 7043579
    Abstract: The present invention provides a data access ring. The data access ring has a plurality of attached processor units (APUs) and a local store associated with each APU. The data access ring has a data command ring, coupled to the plurality of APUs. The data command ring is employable to carry indicia of a selection of one of the plurality of APUs to the APUs. The data access ring also has a data address ring, coupled to the plurality of APUs. The data address ring is further employable to carry indicia of a memory location to the selected APU a predetermined number of clock cycles after the data command ring carries the indicia of the selection of one of the plurality of APUs. The data access ring also has a data transfer ring, coupled to the plurality of APUs. The data transfer ring is employable to transfer data to or from the memory location associated with the APU a predetermined number of clock cycles after the data address ring carries the indicia of the memory location to the selected APU.
    Type: Grant
    Filed: December 5, 2002
    Date of Patent: May 9, 2006
    Assignee: International Business Machines Corporation
    Inventors: Sang Hoo Dhong, Harm Peter Hofstee, John Samuel Liberty, Peichun Peter Liu
  • Publication number: 20040264445
    Abstract: An apparatus which uses channel counters in combination with channel count read instructions as a means of providing information that data in a given channel is valid or has not been previously read. The counter may also, in the situation of the channel being defined as blocking, be used to prevent the unintentional overwriting of data in a register used by the channel or, alternatively, prevent further communications with the device assigned to that channel when a given count occurs. Intelligent external devices may also use channel count read instructions sent to the counting mechanism for reading from and writing to the channel.
    Type: Application
    Filed: June 26, 2003
    Publication date: December 30, 2004
    Applicant: International Business Machines Corporation
    Inventors: Michael Norman Day, Brian King Flachs, Harm Peter Hofstee, Charles Rdy Johns, John Samuel Liberty
  • Publication number: 20040268164
    Abstract: Disclosed is an apparatus which places computer program instructions into instruction channels in accordance with predefined criteria such that at least some external event instructions are placed in a special “blocking channel.” The number of instructions, in a channel, is monitored in channel specific counters. When a computer processor is awaiting a response from an external entity event (in other words, is blocked from proceeding with the operation the PU is attempting), as signified by the blocking counter being at a predetermined value, the entire PU or at least processor auxiliary components that would be idle, such as math logic, while awaiting an external event response, are deactivated to save power until an awaited external event response is received.
    Type: Application
    Filed: June 26, 2003
    Publication date: December 30, 2004
    Applicant: International Business Machines Corporation
    Inventors: Brian King Flachs, John Samuel Liberty, Harm Peter Hofstee
  • Patent number: 6760819
    Abstract: A processor-cache operational scheme and topology within a multi-processor data processing system having a shared lower level cache (or memory) by which the number of coherency busses is reduced and more efficient snoop resolution and coherency operations with the processor caches are provided. A copy of the internal (L1) cache directory is provided within the lower level (L2) cache or memory. The snoop operations and coherency maintenance operations of the L1 directory are completed by comparing the snoop addresses with the address tags of the copy of the L1 directory in the L2 cache. Updates to the coherency states of the copy of the L1 directory are mirrored in the L1 directory and L1 cache. This eliminates the need for the individual coherency buses of each processor that is coupled to the L2 cache and speeds up coherency operations because the snoops do not have to be transmitted to the L1 caches.
    Type: Grant
    Filed: June 29, 2001
    Date of Patent: July 6, 2004
    Assignee: International Business Machines Corporation
    Inventors: Sang Hoo Dhong, Harm Peter Hofstee, Charles Ray Johns, John Samuel Liberty, Thuong Quang Truong
  • Publication number: 20040111546
    Abstract: The present invention provides a data access ring. The data access ring has a plurality of attached processor units (APUs) and a local store associated with each APU. The data access ring has a data command ring, coupled to the plurality of APUs. The data command ring is employable to carry indicia of a selection of one of the plurality of APUs to the APUs. The data access ring also has a data address ring, coupled to the plurality of APUs. The data address ring is further employable to carry indicia of a memory location to the selected APU a predetermined number of clock cycles after the data command ring carries the indicia of the selection of one of the plurality of APUs. The data access ring also has a data transfer ring, coupled to the plurality of APUs. The data transfer ring is employable to transfer data to or from the memory location associated with the APU a predetermined number of clock cycles after the data address ring carries the indicia of the memory location to the selected APU.
    Type: Application
    Filed: December 5, 2002
    Publication date: June 10, 2004
    Applicant: International Business Machines Corporation
    Inventors: Sang Hoo Dhong, Harm Peter Hofstee, John Samuel Liberty, Peichun Peter Liu
  • Publication number: 20030005237
    Abstract: A processor-cache operational scheme and topology within a multi-processor data processing system having a shared lower level cache (or memory) by which the number of coherency busses is reduced and more efficient snoop resolution and coherency operations with the processor caches are provided. A copy of the internal (L1) cache directory is provided within the lower level (L2) cache or memory. The snoop operations and coherency maintenance operations of the L1 directory are completed by comparing the snoop addresses with the address tags of the copy of the L1 directory in the L2 cache. Updates to the coherency states of the copy of the L1 directory are mirrored in the L1 directory and L1 cache. This eliminates the need for the individual coherency buses of each processor that is coupled to the L2 cache and speeds up coherency operations because the snoops do not have to be transmitted to the L1 caches.
    Type: Application
    Filed: June 29, 2001
    Publication date: January 2, 2003
    Applicant: International Business Machines Corp.
    Inventors: Sang Hoo Dhong, Harm Peter Hofstee, Charles Ray Johns, John Samuel Liberty, Thuong Quang Truong
  • Publication number: 20020158885
    Abstract: A method, apparatus, and computer implemented instructions for generating antialiased lines for display in a data processing system. Graphics data is received for display, wherein the graphics data includes primitives defining lines. A gamma correction is applied to the graphics data on a per primitive basis to form antialiased lines. The antialiased lines are displayed.
    Type: Application
    Filed: April 12, 2001
    Publication date: October 31, 2002
    Inventors: Daniel Alan Brokenshire, Bruce David D'Amora, Gordon Clyde Fossum, Charles Ray Johns, John Samuel Liberty, Brad William Michael
  • Patent number: 6421053
    Abstract: Primitives are divided into span groups of 2N spans, and then processed in M×N blocks of pixels, with the pixel blocks preferably being as close to square as possible and therefore optimized for small spans and texture mapping. Each span group is rendered block-by-block in a serpentine manner from an initial or entry block, first in a direction away from the long edge of the primitive and then in a direction towards the long edge. The interpolators include a one-deep stack onto which pixel and texel information for the initial or entry block are pushed before rendering any other blocks within the span group. Blocks or pairs of blocks within different span subgroups of the span group are then alternately rendered, such that rendering zig-zags between the span subgroups as it proceeds to the end of the span group.
    Type: Grant
    Filed: May 24, 1999
    Date of Patent: July 16, 2002
    Assignee: International Business Machines Corporation
    Inventors: Charles Ray Johns, John Samuel Liberty, Brad William Michael, John Fred Spannaus